On 2010.12.14 11:03:53 +0800, Zhenyu Wang wrote: > > Looks from a6963596a13e62f8e65b1cf3403a330ff2db407c, setting > GTT entry on i965-ish totally ignored cached memory flag? > That might break r/w consistent for pages like hw status. >
This should recover that.
From ca8cca3ffe03353c4bacdb30d77ff9c10ff0e4e0 Mon Sep 17 00:00:00 2001
From: Zhenyu Wang <zhen...@linux.intel.com>
Date: Tue, 14 Dec 2010 11:17:32 +0800
Subject: [PATCH] agp/intel: Fix missed cached memory flags setting in GTT entry
write
This fixes regression from a6963596a13e62f8e65b1cf3403a330ff2db407c,
that missed to set cached memory type in GTT entry.
Signed-off-by: Zhenyu Wang <zhen...@linux.intel.com>
---
drivers/char/agp/intel-gtt.c | 8 +++++++-
1 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 326ca2e..c7fe85d 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1138,9 +1138,15 @@ static void i9xx_chipset_flush(void)
static void i965_write_entry(dma_addr_t addr, unsigned int entry,
unsigned int flags)
{
+ int pte_flags = I810_PTE_VALID;
+
/* Shift high bits down */
addr |= (addr >> 28) & 0xf0;
- writel(addr | I810_PTE_VALID, intel_private.gtt + entry);
+
+ if (flags == AGP_USER_CACHED_MEMORY)
+ pte_flags |= I830_PTE_SYSTEM_CACHED;
+
+ writel(addr | pte_flags, intel_private.gtt + entry);
}
static bool gen6_check_flags(unsigned int flags)
--
1.7.1
--
Open Source Technology Center, Intel ltd.
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