On Wed, Apr 13, 2011 at 07:35:52PM +0100, Chris Wilson wrote: > ... or if we will need to perform a cache-flush on the object anyway. > Unless, of course, we need to use a fence register to perform tiling > operations during the transfer (in which case we are no longer on a > chipset for which we need to be extra careful not to write through the > GTT to a snooped page).
So either we are on snb and there gtt writes should work on llc cached objects (otherwise we'll have a giant problem with uploads to tiled buffers). On the other hand on pre-gen6 tiling on snooped mem doesn't work and we have a few other restrictions like this here. So for that userspace needs to be aware of what's going on, anyway. Hence we might as well SIGBUS/disallow gtt mappings for such vmapped buffers and teach userspace to use the cpu mappings (again). I don't know but maybe using snooped buffers to directly write to vbos and stuff like that is better on snb. Currently we're using pwrite everywhere, so again a userspace changes seems required, why not use cpu mappings directly? Hence I'd like to weasel myself out from reviewing this: Do we really need this complexity? -Daniel -- Daniel Vetter Mail: [email protected] Mobile: +41 (0)79 365 57 48 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
