GFX_MODE controls important behavior like PPGTT, run lists, and TLB
invalidate behavior. On the SDV I'm using, the TLB invalidation mode
was defaulting to "pipe control only" which meant regular MI_FLUSHes
wouldn't actually flush the TLB, leading to all sorts of stale data
getting used.
So initialize it to 0 at ring buffer init time until we actually use
PIPE_CONTROL for TLB invalidation.
Signed-off-by: Jesse Barnes <jbar...@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
2 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7033e01..9f3938c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -382,6 +382,8 @@
#define GFX_PSMI_GRANULARITY (1<<10)
#define GFX_PPGTT_ENABLE (1<<9)
+#define GFX_MODE_GEN7 0x0229c
+
#define SCPD0 0x0209c /* 915+ only */
#define IER 0x020a0
#define IIR 0x020a4
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 47b9b27..80fea69 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1293,6 +1293,8 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
ring->add_request = gen6_add_request;
ring->irq_get = gen6_render_ring_get_irq;
ring->irq_put = gen6_render_ring_put_irq;
+ if (IS_GEN7(dev))
+ I915_WRITE(GFX_MODE_GEN7, 0xffff0000);
} else if (IS_GEN5(dev)) {
ring->add_request = pc_render_add_request;
ring->get_seqno = pc_render_get_seqno;
--
1.7.4.1
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