On Mon, Nov 28, 2011 at 10:24:52PM +0100, Daniel Vetter wrote:
> v2: Don't try to enable ppgtt on pre-snb.
>
> Signed-off-by: Daniel Vetter <daniel.vet...@ffwll.ch>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 2 ++
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_gem.c | 39
> +++++++++++++++++++++++++++++++++++++++
> 3 files changed, 42 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index f12b43e..c7cf881 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -698,6 +698,8 @@ int i915_reset(struct drm_device *dev, u8 flags)
> if (HAS_BLT(dev))
> dev_priv->ring[BCS].init(&dev_priv->ring[BCS]);
>
> + i915_gem_init_ppgtt(dev);
> +
> mutex_unlock(&dev->struct_mutex);
> drm_irq_uninstall(dev);
> drm_mode_config_reset(dev);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 5db3b84..0d228d2 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1228,6 +1228,7 @@ int __must_check i915_gem_object_set_domain(struct
> drm_i915_gem_object *obj,
> int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
> int __must_check i915_gem_init_hw(struct drm_device *dev);
> void i915_gem_init_swizzling(struct drm_device *dev);
> +void i915_gem_init_ppgtt(struct drm_device *dev);
> void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
> void i915_gem_do_init(struct drm_device *dev,
> unsigned long start,
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 593aa60..e1d7852 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -3772,6 +3772,43 @@ void i915_gem_init_swizzling(struct drm_device *dev)
> DISP_TILE_SURFACE_SWIZZLING);
>
> }
> +
> +void i915_gem_init_ppgtt(struct drm_device *dev)
> +{
> + drm_i915_private_t *dev_priv = dev->dev_private;
> + uint32_t pd_offset;
> + struct intel_ring_buffer *ring;
> + int i;
> +
> + if (!HAS_ALIASING_PPGTT(dev))
> + return;
> +
> + pd_offset = dev_priv->mm.aliasing_ppgtt->pd_offset;
> + pd_offset /= 64; /* in cachelines, */
> + pd_offset <<= 16;
> +
> + if (INTEL_INFO(dev)->gen == 6) {
> + uint32_t ecochk = I915_READ(GAM_ECOCHK);
> + I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
> + ECOCHK_PPGTT_CACHE64B);
> + I915_WRITE(GFX_MODE, GFX_MODE_ENABLE(GFX_PPGTT_ENABLE));
> + } else if (INTEL_INFO(dev)->gen >= 7) {
> + I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
> + /* GFX_MODE is per-ring on gen7+ */
> + }
> +
> + for (i = 0; i < I915_NUM_RINGS; i++) {
> + ring = &dev_priv->ring[i];
> +
> + if (INTEL_INFO(dev)->gen >= 7)
> + I915_WRITE(RING_MODE_GEN7(ring),
> + GFX_MODE_ENABLE(GFX_PPGTT_ENABLE));
> +
> + I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
> + I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
> + }
> +}
> +
> int
> i915_gem_init_hw(struct drm_device *dev)
> {
> @@ -3798,6 +3835,8 @@ i915_gem_init_hw(struct drm_device *dev)
>
> dev_priv->next_seqno = 1;
>
> + i915_gem_init_ppgtt(dev);
> +
> return 0;
>
> cleanup_bsd_ring:
Maybe through some DRM_INFOs in here for later debugging to see if we
failed in setting up the page tables?
Also, does this work across resume and reset?
Ben
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
