<#part sign=pgpmime> On Thu, 29 Mar 2012 13:44:28 +0100, Chris Wilson <[email protected]> wrote:
> In conjunction with bits Power Sequence Progress field and Power Cycle > Delay Active, this bit set to a one indicates that the panel is > currently powered up or is currently in the power down sequence and it > is unsafe to change the timing, port, and DPLL registers for the pipe or > transcoder that is assigned to the panel output. The theory was that as we don't touch the DPLL and only modify the scaler, that the panel wouldn't care. I wonder what's confusing this one... -- [email protected] _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
