On Sat, Mar 31, 2012 at 11:21:58AM +0200, Daniel Vetter wrote:
> Contrary to the other clock gating w/a in GEN6_UCGCTL1, this one is
> actually documented in Bspec, vol1g "GT Interface Registers [SNB]",
> Section 1.5.1 "UCGCTL1 - Unit Level Clock Gating Control 1".
> 
> Supposedly this can prevent hangs on the media ring.
> 
> Signed-Off-by: Daniel Vetter <daniel.vet...@ffwll.ch>
Reviewed-by: Ben Widawsky <b...@bwidawsk.net>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Reply via email to