This is a hack to make sure CPU eDP mode sets avoid allocating a PCH PLL.
Signed-off-by: Jesse Barnes <jbar...@virtuousgeek.org>
---
drivers/gpu/drm/i915/intel_display.c | 2 ++
drivers/gpu/drm/i915/intel_dp.c | 4 ++++
2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 33aaad3..0b5f843 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6225,6 +6225,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
fp == I915_READ(PCH_FP0(1))) {
intel_crtc->use_pll_a = false;
DRM_DEBUG_KMS("using pipe b dpll\n");
+ } else if (is_cpu_edp) {
+ DRM_DEBUG_KMS("CPU eDP, no PCH PLL needed\n");
} else {
DRM_DEBUG_KMS("no matching PLL configuration for pipe
2\n");
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 6346b29..89b326f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2417,6 +2417,10 @@ intel_dp_init(struct drm_device *dev, int output_reg)
}
intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
+
+ if (IS_IVYBRIDGE(dev) && output_reg == DP_A)
+ intel_encoder->crtc_mask = (1 << 2);
+
connector->interlace_allowed = true;
connector->doublescan_allowed = 0;
--
1.7.4.1
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