On Tue, Oct 11, 2016 at 02:21:48PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
>
> Saves 472 bytes of .rodata strings.
>
> v2: Add parantheses around dev_priv. (Ville Syrjala)
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
Reviewed-by: David Weinehall <david.weineh...@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_gem_stolen.c | 5 +++--
> drivers/gpu/drm/i915/i915_suspend.c | 4 ++--
> drivers/gpu/drm/i915/intel_crt.c | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 40
> ++++++++++++++++++----------------
> drivers/gpu/drm/i915/intel_dp.c | 2 +-
> drivers/gpu/drm/i915/intel_hdmi.c | 4 ++--
> drivers/gpu/drm/i915/intel_pm.c | 4 ++--
> 8 files changed, 33 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c264e703b686..f54465ea2f44 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2649,7 +2649,7 @@ struct drm_i915_cmd_table {
> #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
> #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
> #define IS_GM45(dev_priv) (INTEL_DEVID(dev_priv) == 0x2A42)
> -#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
> +#define IS_G4X(dev_priv) ((dev_priv)->info.is_g4x)
> #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
> #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
> #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
> diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c
> b/drivers/gpu/drm/i915/i915_gem_stolen.c
> index 3508120b8c90..d1b40bce0249 100644
> --- a/drivers/gpu/drm/i915/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
> @@ -204,7 +204,8 @@ static unsigned long i915_stolen_to_physical(struct
> drm_device *dev)
> return 0;
>
> /* make sure we don't clobber the GTT if it's within stolen memory */
> - if (INTEL_INFO(dev)->gen <= 4 && !IS_G33(dev) && !IS_G4X(dev)) {
> + if (INTEL_GEN(dev_priv) <= 4 && !IS_G33(dev_priv) &&
> + !IS_G4X(dev_priv)) {
> struct {
> u32 start, end;
> } stolen[2] = {
> @@ -437,7 +438,7 @@ int i915_gem_init_stolen(struct drm_device *dev)
> case 3:
> break;
> case 4:
> - if (IS_G4X(dev))
> + if (IS_G4X(dev_priv))
> g4x_get_stolen_reserved(dev_priv, &reserved_base,
> &reserved_size);
> break;
> diff --git a/drivers/gpu/drm/i915/i915_suspend.c
> b/drivers/gpu/drm/i915/i915_suspend.c
> index a0af170062b1..7870856fccd0 100644
> --- a/drivers/gpu/drm/i915/i915_suspend.c
> +++ b/drivers/gpu/drm/i915/i915_suspend.c
> @@ -38,7 +38,7 @@ static void i915_save_display(struct drm_device *dev)
> dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
>
> /* save FBC interval */
> - if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
> + if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
> dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
> }
>
> @@ -54,7 +54,7 @@ static void i915_restore_display(struct drm_device *dev)
> intel_fbc_global_disable(dev_priv);
>
> /* restore FBC interval */
> - if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
> + if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
> I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
>
> i915_redisable_vga(dev);
> diff --git a/drivers/gpu/drm/i915/intel_crt.c
> b/drivers/gpu/drm/i915/intel_crt.c
> index d4388c03b4da..d456786f5813 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -771,7 +771,7 @@ static int intel_crt_get_modes(struct drm_connector
> *connector)
>
> i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
> ret = intel_crt_ddc_get_modes(connector, i2c);
> - if (ret || !IS_G4X(dev))
> + if (ret || !IS_G4X(dev_priv))
> goto out;
>
> /* Try to probe digital port for output in DVI-I -> VGA mode. */
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 636e5572b996..bf871b565549 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3071,7 +3071,7 @@ static void i9xx_update_primary_plane(struct drm_plane
> *primary,
> fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
> dspcntr |= DISPPLANE_TILED;
>
> - if (IS_G4X(dev))
> + if (IS_G4X(dev_priv))
> dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
>
> intel_add_fb_offsets(&x, &y, plane_state, 0);
> @@ -7226,7 +7226,7 @@ static int intel_crtc_compute_config(struct intel_crtc
> *crtc,
> /* Cantiga+ cannot handle modes with a hsync front porch of 0.
> * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
> */
> - if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
> + if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
> adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
> return -EINVAL;
>
> @@ -7540,7 +7540,7 @@ static unsigned int intel_hpll_vco(struct drm_device
> *dev)
> /* FIXME other chipsets? */
> if (IS_GM45(dev_priv))
> vco_table = ctg_vco;
> - else if (IS_G4X(dev))
> + else if (IS_G4X(dev_priv))
> vco_table = elk_vco;
> else if (IS_CRESTLINE(dev))
> vco_table = cl_vco;
> @@ -8174,7 +8174,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,
> dpll |= (1 << (clock->p1 - 1)) <<
> DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
> else {
> dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
> - if (IS_G4X(dev) && reduced_clock)
> + if (IS_G4X(dev_priv) && reduced_clock)
> dpll |= (1 << (reduced_clock->p1 - 1)) <<
> DPLL_FPA1_P1_POST_DIV_SHIFT;
> }
> switch (clock->p2) {
> @@ -8416,7 +8416,8 @@ static void i9xx_set_pipeconf(struct intel_crtc
> *intel_crtc)
> pipeconf |= PIPECONF_DOUBLE_WIDE;
>
> /* only g4x and later have fancy bpc/dither controls */
> - if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
> + IS_CHERRYVIEW(dev_priv)) {
> /* Bspec claims that we can't use dithering for 30bpp pipes. */
> if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp
> != 30)
> pipeconf |= PIPECONF_DITHER_EN |
> @@ -8833,7 +8834,8 @@ static bool i9xx_get_pipe_config(struct intel_crtc
> *crtc,
> if (!(tmp & PIPECONF_ENABLE))
> goto out;
>
> - if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
> + IS_CHERRYVIEW(dev_priv)) {
> switch (tmp & PIPECONF_BPC_MASK) {
> case PIPECONF_6BPC:
> pipe_config->pipe_bpp = 18;
> @@ -11582,7 +11584,7 @@ static bool __pageflip_finished_cs(struct intel_crtc
> *crtc,
> * really needed there. But since ctg has the registers,
> * include it in the check anyway.
> */
> - if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
> + if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
> return true;
>
> /*
> @@ -12245,7 +12247,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
>
> atomic_inc(&intel_crtc->unpin_work_count);
>
> - if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
> + if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
> work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
>
> if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> @@ -12705,15 +12707,16 @@ static int
> compute_baseline_pipe_bpp(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config)
> {
> - struct drm_device *dev = crtc->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct drm_atomic_state *state;
> struct drm_connector *connector;
> struct drm_connector_state *connector_state;
> int bpp, i;
>
> - if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
> + if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
> + IS_CHERRYVIEW(dev_priv)))
> bpp = 10*3;
> - else if (INTEL_INFO(dev)->gen >= 5)
> + else if (INTEL_GEN(dev_priv) >= 5)
> bpp = 12*3;
> else
> bpp = 8*3;
> @@ -13404,7 +13407,7 @@ intel_pipe_config_compare(struct drm_device *dev,
> PIPE_CONF_CHECK_X(dsi_pll.ctrl);
> PIPE_CONF_CHECK_X(dsi_pll.div);
>
> - if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
> + if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
> PIPE_CONF_CHECK_I(pipe_bpp);
>
> PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
> @@ -14966,7 +14969,7 @@ static struct drm_plane
> *intel_primary_plane_create(struct drm_device *dev,
> intel_primary_formats,
> num_formats,
> DRM_PLANE_TYPE_PRIMARY,
> "plane 1%c", pipe_name(pipe));
> - else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
> + else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
> ret = drm_universal_plane_init(dev, &primary->base, 0,
> &intel_plane_funcs,
> intel_primary_formats,
> num_formats,
> @@ -15527,12 +15530,12 @@ static void intel_setup_outputs(struct drm_device
> *dev)
> if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
> DRM_DEBUG_KMS("probing SDVOB\n");
> found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
> - if (!found && IS_G4X(dev)) {
> + if (!found && IS_G4X(dev_priv)) {
> DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
> intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
> }
>
> - if (!found && IS_G4X(dev))
> + if (!found && IS_G4X(dev_priv))
> intel_dp_init(dev, DP_B, PORT_B);
> }
>
> @@ -15545,16 +15548,15 @@ static void intel_setup_outputs(struct drm_device
> *dev)
>
> if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
>
> - if (IS_G4X(dev)) {
> + if (IS_G4X(dev_priv)) {
> DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
> intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
> }
> - if (IS_G4X(dev))
> + if (IS_G4X(dev_priv))
> intel_dp_init(dev, DP_C, PORT_C);
> }
>
> - if (IS_G4X(dev) &&
> - (I915_READ(DP_D) & DP_DETECTED))
> + if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
> intel_dp_init(dev, DP_D, PORT_D);
> } else if (IS_GEN2(dev))
> intel_dvo_init(dev);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index b6c8b25ee1d4..dfc93cc11a13 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1341,7 +1341,7 @@ intel_dp_set_clock(struct intel_encoder *encoder,
> const struct dp_link_dpll *divisor = NULL;
> int i, count = 0;
>
> - if (IS_G4X(dev)) {
> + if (IS_G4X(dev_priv)) {
> divisor = gen4_dpll;
> count = ARRAY_SIZE(gen4_dpll);
> } else if (HAS_PCH_SPLIT(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> b/drivers/gpu/drm/i915/intel_hdmi.c
> index f6562451c47e..c7d9cddf4e3e 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1889,7 +1889,7 @@ void intel_hdmi_init_connector(struct
> intel_digital_port *intel_dig_port,
> intel_hdmi->write_infoframe = vlv_write_infoframe;
> intel_hdmi->set_infoframes = vlv_set_infoframes;
> intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
> - } else if (IS_G4X(dev)) {
> + } else if (IS_G4X(dev_priv)) {
> intel_hdmi->write_infoframe = g4x_write_infoframe;
> intel_hdmi->set_infoframes = g4x_set_infoframes;
> intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
> @@ -1996,7 +1996,7 @@ void intel_hdmi_init(struct drm_device *dev,
> * to work on real hardware. And since g4x can send infoframes to
> * only one port anyway, nothing is lost by allowing it.
> */
> - if (IS_G4X(dev))
> + if (IS_G4X(dev_priv))
> intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
>
> intel_dig_port->port = port;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3ba9502cf2c2..2c5dcd3ba2c2 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -326,7 +326,7 @@ void intel_set_memory_cxsr(struct drm_i915_private
> *dev_priv, bool enable)
> I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
> POSTING_READ(FW_BLC_SELF_VLV);
> dev_priv->wm.vlv.cxsr = enable;
> - } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
> + } else if (IS_G4X(dev_priv) || IS_CRESTLINE(dev_priv)) {
> I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
> POSTING_READ(FW_BLC_SELF);
> } else if (IS_PINEVIEW(dev)) {
> @@ -7776,7 +7776,7 @@ void intel_init_pm(struct drm_device *dev)
> dev_priv->display.update_wm = NULL;
> } else
> dev_priv->display.update_wm = pineview_update_wm;
> - } else if (IS_G4X(dev)) {
> + } else if (IS_G4X(dev_priv)) {
> dev_priv->display.update_wm = g4x_update_wm;
> } else if (IS_GEN4(dev)) {
> dev_priv->display.update_wm = i965_update_wm;
> --
> 2.7.4
>
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