Since Broxton has same FBC block as BDW+ let's assume it also
don't have access to the stolen usable range.
FBC is currently not saving power on Broxton and I believe
the compression threshold is limited to 1x.
v2: duh! inverted check. (Thanks Marc)
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Marc Herbert <marc.herb...@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>
---
drivers/gpu/drm/i915/intel_fbc.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index cbe2ebd..214b2de 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -530,12 +530,11 @@ static int find_compression_threshold(struct
drm_i915_private *dev_priv,
int ret;
u64 end;
- /* The FBC hardware for BDW/SKL doesn't have access to the stolen
+ /* The FBC hardware for gen8+ doesn't have access to the stolen
* reserved range size, so it always assumes the maximum (8mb) is used.
* If we enable FBC using a CFB on that memory range we'll get FIFO
* underruns, even if that range is not reserved by the BIOS. */
- if (IS_BROADWELL(dev_priv) ||
- IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
+ if (INTEL_INFO(dev_priv)->gen >= 8)
end = ggtt->stolen_size - 8 * 1024 * 1024;
else
end = ggtt->stolen_usable_size;
--
1.9.1
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