On Fri, Jan 27, 2017 at 03:44:27PM +0100, Arthur Heymans wrote: > This is according to Mobile Intel® 945 Express Chipset > Family datasheet. > > Signed-off-by: Arthur Heymans <art...@aheymans.xyz> > --- > drivers/gpu/drm/i915/i915_reg.h | 2 +- > drivers/gpu/drm/i915/intel_display.c | 27 +++++++++++++++++++++++++-- > 2 files changed, 26 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 70d96162def6..c3141e40d938 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -114,7 +114,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > #define GCFGC 0xf0 /* 915+ only */ > #define GC_LOW_FREQUENCY_ENABLE (1 << 7) > #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) > -#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) > +#define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4) > #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4) > #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4) > #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4) > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 81c11499bcf0..307fc62e7c70 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -7389,6 +7389,26 @@ static int i945_get_display_clock_speed(struct > drm_device *dev) > return 400000; > } > > +static int 945gm_get_display_clock_speed(struct drm_device *dev) > +{ > + struct pci_dev *pdev = dev->pdev; > + u16 gcfgc = 0; > + > + pci_read_config_word(pdev, GCFGC, &gcfgc); > + > + if (gcfgc & GC_LOW_FREQUENCY_ENABLE) > + return 133333; > + else { > + switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { > + case GC_DISPLAY_CLOCK_333_320_MHZ: > + return 320000;
That indeed is what the docs say. The code is tantalizingly close to the 915gm code now, so maybe we could share it with a simple if (IS_915GM(dev_priv)) return 320000; else return 333333; ? Now if someone could figure out where to dig up the DDR and FSB clocks we could also fix up the 190 vs. 200 MHz case... > + default: > + case GC_DISPLAY_CLOCK_190_200_MHZ: > + return 200000; > + } > + } > +} > + > static int i915_get_display_clock_speed(struct drm_device *dev) > { > return 333333; > @@ -7435,7 +7455,7 @@ static int i915gm_get_display_clock_speed(struct > drm_device *dev) > return 133333; > else { > switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { > - case GC_DISPLAY_CLOCK_333_MHZ: > + case GC_DISPLAY_CLOCK_333_320_MHZ: > return 333333; > default: > case GC_DISPLAY_CLOCK_190_200_MHZ: > @@ -15991,9 +16011,12 @@ void intel_init_display_hooks(struct > drm_i915_private *dev_priv) > else if (IS_I915G(dev_priv)) > dev_priv->display.get_display_clock_speed = > i915_get_display_clock_speed; > - else if (IS_I945GM(dev_priv) || IS_845G(dev_priv)) > + else if (IS_845G(dev_priv)) > dev_priv->display.get_display_clock_speed = > i9xx_misc_get_display_clock_speed; > + else if (IS_I945GM(dev_priv)) > + dev_priv->display.get_display_clock_speed = > + 954gm_get_display_clock_speed; > else if (IS_I915GM(dev_priv)) > dev_priv->display.get_display_clock_speed = > i915gm_get_display_clock_speed; > -- > 2.11.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx