On Wed, Feb 08, 2017 at 06:04:20PM +0000, Tvrtko Ursulin wrote: > @@ -868,10 +869,11 @@ void __i915_add_request(struct drm_i915_gem_request > *request, bool flush_caches) > * GPU processing the request, we never over-estimate the > * position of the ring's HEAD. > */ > - err = intel_ring_begin(request, engine->emit_breadcrumb_sz); > - GEM_BUG_ON(err); > - request->postfix = ring->tail; > - ring->tail += engine->emit_breadcrumb_sz * sizeof(u32); > + out = intel_ring_begin(request, engine->emit_breadcrumb_sz); > + GEM_BUG_ON(IS_ERR(out)); > + GEM_BUG_ON(engine->emit_breadcrumb_sz * sizeof(u32) > ring->tail); > + request->postfix = ring->tail - > + engine->emit_breadcrumb_sz * sizeof(u32);
request->postfix = intel_ring_offset(req, out); ? -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
