Chris Wilson <ch...@chris-wilson.co.uk> writes:
> We are required to reload the TLBs around context switches
> (MI_SET_CONTEXT specifically) and the recommendation is do that before
> the MI_SET_CONTEXT so that it is serialised with the switch and not
> forgotten:
>
> [DevSNB] If Flush TLB invalidation Mode is enabled it’s the driver’s
> responsibility to invalidate the TLBs at least once after the previous
> context switch after any GTT mappings changed (including new GTT entries).
> This can be done by a pipeline PIPE_CONTROL with TLB inv bit set
> immediately before MI_SET_CONTEXT.
>
> However, we already do an unconditional TLB invalidate before every
> batch so this condition is satifisfied.
>
> Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuopp...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_gem_context.c | 11 -----------
> 1 file changed, 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
> b/drivers/gpu/drm/i915/i915_gem_context.c
> index 99c46f4dbde6..521e6f4705b1 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -607,17 +607,6 @@ mi_set_context(struct drm_i915_gem_request *req, u32
> hw_flags)
> 0;
> int len;
>
> - /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
> - * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
> - * explicitly, so we rely on the value at ring init, stored in
> - * itlb_before_ctx_switch.
> - */
> - if (IS_GEN6(dev_priv)) {
> - int ret = engine->emit_flush(req, EMIT_INVALIDATE);
> - if (ret)
> - return ret;
> - }
> -
> /* These flags are for resource streamer on HSW+ */
> if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8)
> flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN);
> --
> 2.11.0
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
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