Don't mark pdps clear if never do the necessary actions
with the hardware to make them clear.

v2: totally get rid of confusing ppgtt bool (Chris)

Signed-off-by: Mika Kuoppala <mika.kuopp...@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 21 ++++++++++-----------
 1 file changed, 10 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index f9a8545..4ae9f1f 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1319,9 +1319,8 @@ static int intel_logical_ring_emit_pdps(struct 
drm_i915_gem_request *req)
 
 static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
                              u64 offset, u32 len,
-                             unsigned int dispatch_flags)
+                             const unsigned int flags)
 {
-       bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
        u32 *cs;
        int ret;
 
@@ -1332,13 +1331,12 @@ static int gen8_emit_bb_start(struct 
drm_i915_gem_request *req,
         * not idle). PML4 is allocated during ppgtt init so this is
         * not needed in 48-bit.*/
        if (req->ctx->ppgtt &&
-           (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) 
{
-               if (!i915_vm_is_48bit(&req->ctx->ppgtt->base) &&
-                   !intel_vgpu_active(req->i915)) {
-                       ret = intel_logical_ring_emit_pdps(req);
-                       if (ret)
-                               return ret;
-               }
+           (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings) 
&&
+           !i915_vm_is_48bit(&req->ctx->ppgtt->base) &&
+           !intel_vgpu_active(req->i915)) {
+               ret = intel_logical_ring_emit_pdps(req);
+               if (ret)
+                       return ret;
 
                req->ctx->ppgtt->pd_dirty_rings &= 
~intel_engine_flag(req->engine);
        }
@@ -1348,8 +1346,9 @@ static int gen8_emit_bb_start(struct drm_i915_gem_request 
*req,
                return PTR_ERR(cs);
 
        /* FIXME(BDW): Address space and security selectors. */
-       *cs++ = MI_BATCH_BUFFER_START_GEN8 | (ppgtt << 8) | (dispatch_flags &
-               I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0);
+       *cs++ = MI_BATCH_BUFFER_START_GEN8 |
+               (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)) |
+               (flags & I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0);
        *cs++ = lower_32_bits(offset);
        *cs++ = upper_32_bits(offset);
        *cs++ = MI_NOOP;
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Reply via email to