To enable 64K pages we need to set the intermediate-page-size(IPS) bit
of the pde, therefore a page table is said to be either operating in 64K
or 4K mode. To accommodate this vm placement restriction we introduce a
color for pages and corresponding color_adjust callback. Currently this
only considers the full 48bit ppgtt case.
Signed-off-by: Matthew Auld <matthew.a...@intel.com>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 25 +++++++++++++++++++++++++
drivers/gpu/drm/i915/i915_gem_gtt.h | 6 ++++++
drivers/gpu/drm/i915/i915_vma.c | 2 ++
3 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 6b70332cafac..0fb67941ba6b 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1331,6 +1331,28 @@ static int gen8_preallocate_top_level_pdp(struct
i915_hw_ppgtt *ppgtt)
return -ENOMEM;
}
+static void i915_page_color_adjust(const struct drm_mm_node *node,
+ unsigned long color,
+ u64 *start,
+ u64 *end)
+{
+ GEM_BUG_ON(color & ~I915_GTT_PAGE_SIZE_MASK);
+
+ if (!(color & (I915_GTT_PAGE_SIZE_64K | I915_GTT_PAGE_SIZE)))
+ return;
+
+ GEM_BUG_ON(node->allocated && node->color & ~I915_GTT_PAGE_SIZE_MASK);
+
+ if (i915_color_differs(node, color))
+ *start = roundup(*start, 1 << GEN8_PDE_SHIFT);
+
+ node = list_next_entry(node, node_list);
+ if (i915_color_differs(node, color))
+ *end = rounddown(*end, 1 << GEN8_PDE_SHIFT);
+
+ GEM_BUG_ON(node->allocated && node->color & ~I915_GTT_PAGE_SIZE_MASK);
+}
+
/*
* GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
* with a net effect resembling a 2-level page table in normal x86 terms. Each
@@ -1371,6 +1393,9 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
ppgtt->base.allocate_va_range = gen8_ppgtt_alloc_4lvl;
ppgtt->base.insert_entries = gen8_ppgtt_insert_4lvl;
ppgtt->base.clear_range = gen8_ppgtt_clear_4lvl;
+
+ if (INTEL_INFO(dev_priv)->page_size_mask &
I915_GTT_PAGE_SIZE_64K)
+ ppgtt->base.mm.color_adjust = i915_page_color_adjust;
} else {
ret = __pdp_init(&ppgtt->base, &ppgtt->pdp);
if (ret)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 8d7436105718..e1b8d1c4734b 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -352,6 +352,12 @@ i915_uses_cache_coloring(const struct i915_address_space
*vm)
}
static inline bool
+i915_uses_page_coloring(const struct i915_address_space *vm)
+{
+ return vm->mm.color_adjust && !i915_is_ggtt(vm);
+}
+
+static inline bool
i915_vm_is_48bit(const struct i915_address_space *vm)
{
return (vm->total - 1) >> 32;
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 0d289cbc0123..ee5395e744e1 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -469,6 +469,8 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64
alignment, u64 flags)
if (i915_uses_cache_coloring(vma->vm))
color = obj->cache_level;
+ else if (i915_uses_page_coloring(vma->vm))
+ color = obj->page_size;
if (flags & PIN_OFFSET_FIXED) {
u64 offset = flags & PIN_OFFSET_MASK;
--
2.9.3
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