v1: Updated tasks and frequency post reset.
Added DFPS param update for MAX_FPS and FPS Stall.
v2-v3: Rebase.
v4: Updated with GuC firmware v9.
v5: Rebase. Replaced H2G interrupts for parameter override with memory
setup with required parameters.
v6: Moved task override to intel_slpc_init. Added override of min frequency
to Rpe. Commit subject update.
Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 2 +-
drivers/gpu/drm/i915/intel_slpc.c | 46 +++++++++++++++++++++++++++++++++++++++
3 files changed, 48 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 51228fe..f2fc0fe 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1816,6 +1816,7 @@ bool chv_phy_powergate_ch(struct drm_i915_private
*dev_priv, enum dpio_phy phy,
void gen6_rps_boost(struct drm_i915_private *dev_priv,
struct intel_rps_client *rps,
unsigned long submitted);
+void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv);
void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
void vlv_wm_get_hw_state(struct drm_device *dev);
void ilk_wm_get_hw_state(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 73c4cd3..32be190 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5569,7 +5569,7 @@ int sanitize_rc6_option(struct drm_i915_private
*dev_priv, int enable_rc6)
return INTEL_RC6_ENABLE;
}
-static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
+void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
{
/* All of these values are in units of 50MHz */
diff --git a/drivers/gpu/drm/i915/intel_slpc.c
b/drivers/gpu/drm/i915/intel_slpc.c
index 79b7954..ca5ec09 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -501,6 +501,48 @@ static void slpc_shared_data_init(struct drm_i915_private
*dev_priv)
data->platform_info.Pe_freq = val >> 40;
data->platform_info.Pn_freq = val >> 48;
+ /* Enable only GTPERF task, Disable others */
+ val = SLPC_PARAM_TASK_ENABLED;
+ slpc_mem_task_control(data, val,
+ SLPC_PARAM_TASK_ENABLE_GTPERF,
+ SLPC_PARAM_TASK_DISABLE_GTPERF);
+
+ val = SLPC_PARAM_TASK_DISABLED;
+ slpc_mem_task_control(data, val,
+ SLPC_PARAM_TASK_ENABLE_BALANCER,
+ SLPC_PARAM_TASK_DISABLE_BALANCER);
+
+ slpc_mem_task_control(data, val,
+ SLPC_PARAM_TASK_ENABLE_DCC,
+ SLPC_PARAM_TASK_DISABLE_DCC);
+
+ slpc_mem_set_param(data, SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS, 0);
+
+ slpc_mem_set_param(data, SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING,
+ 0);
+
+ slpc_mem_set_param(data, SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING,
+ 0);
+
+ slpc_mem_set_param(data,
+ SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO,
+ 0);
+
+ slpc_mem_set_param(data, SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE, 0);
+
+ slpc_mem_set_param(data,
+ SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE,
+ 0);
+
+ slpc_mem_set_param(data,
+ SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+ intel_gpu_freq(dev_priv,
+ dev_priv->rps.efficient_freq));
+ slpc_mem_set_param(data,
+ SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+ intel_gpu_freq(dev_priv,
+ dev_priv->rps.efficient_freq));
+
kunmap_atomic(data);
}
@@ -862,6 +904,10 @@ void intel_slpc_init(struct drm_i915_private *dev_priv)
dev_priv->guc.slpc.active = false;
+ mutex_lock(&dev_priv->rps.hw_lock);
+ gen6_init_rps_frequencies(dev_priv);
+ mutex_unlock(&dev_priv->rps.hw_lock);
+
/* Allocate shared data structure */
vma = dev_priv->guc.slpc.vma;
if (!vma) {
--
1.9.1
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