BDW supports RCS slices powering on/off. To do that we need make_rpcs
executed on BDW to flash slices configuration.
Change-Id: Ia80b1be329bedc57cc61078ea18ecb3d2580c16a
Signed-off-by: Dmitry Rogozhkin <dmitry.v.rogozh...@intel.com>
CC: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
CC: Zhipeng Gong <zhipeng.g...@intel.com>
CC: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
CC: Chris Wilson <ch...@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 2a1b641..bc650df 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1732,7 +1732,7 @@ int logical_xcs_ring_init(struct intel_engine_cs *engine)
* No explicit RPCS request is needed to ensure full
* slice/subslice/EU enablement prior to Gen9.
*/
- if (INTEL_GEN(dev_priv) < 9)
+ if (INTEL_GEN(dev_priv) < 8)
return 0;
/*
--
1.8.3.1
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