From: Robert Bragg <rob...@sixbynine.org>
Assuming a uniform mask across all slices, this enables userspace to
determine the specific sub slices enabled. This information is required,
for example, to be able to analyse some OA counter reports where the
counter configuration depends on the HW sub slice configuration.
v2: Rebase
Signed-off-by: Robert Bragg <rob...@sixbynine.org>
Reviewed-by: Matthew Auld <matthew.a...@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 5 +++++
include/uapi/drm/i915_drm.h | 5 +++++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 59a0f9de36b0..f9cadfbbb69f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -363,6 +363,11 @@ static int i915_getparam(struct drm_device *dev, void
*data,
if (!value)
return -ENODEV;
break;
+ case I915_PARAM_SUBSLICE_MASK:
+ value = INTEL_INFO(dev_priv)->sseu.subslice_mask;
+ if (!value)
+ return -ENODEV;
+ break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 25695c3d9a76..464547d08173 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -421,6 +421,11 @@ typedef struct drm_i915_irq_wait {
/* Query the mask of slices available for this system */
#define I915_PARAM_SLICE_MASK 46
+/* Assuming it's uniform for each slice, this queries the mask of subslices
+ * per-slice for this system.
+ */
+#define I915_PARAM_SUBSLICE_MASK 47
+
typedef struct drm_i915_getparam {
__s32 param;
/*
--
2.11.0
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