Em Qua, 2017-07-19 às 00:27 +0530, Praveen Paneri escreveu:
> When FBC is enabled for linear, legacy Y-tiled and Yf-tiled
> surfaces on gen9, the cfb stride must be programmed by SW as
>
> cfb_stride = ceiling[(at least plane width in pixels)/
> (32 * compression limit factor)] * 8
>
> v2: Minor fix for a build error
> v3: Fixed subject, register name and platform check (Ville)
> v4: Added WA details in comment (Paulo)
> v5:
> - Read modified reg write to preserve other bit values (Paulo)
> - Store modified stride value in reg_params (Paulo)
> - Keep GLK out of the WA (Paulo)
>
> Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
> Signed-off-by: Praveen Paneri <praveen.pan...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_fbc.c | 19 +++++++++++++++++++
> 2 files changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index c712d01..9e65f34 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6710,6 +6710,9 @@ enum {
> #define CHICKEN_MISC_2 _MMIO(0x42084)
> #define COMP_PWR_DOWN (1 << 23)
>
> +#define CHICKEN_MISC_4 _MMIO(0x4208c)
> +#define FBC_STRIDE_OVERRIDE (1<<13)
> +
> #define _CHICKEN_PIPESL_1_A 0x420b0
> #define _CHICKEN_PIPESL_1_B 0x420b4
> #define HSW_FBCQ_DIS (1 << 22)
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c
> b/drivers/gpu/drm/i915/intel_fbc.c
> index 860b8c2..251d3f4 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -288,9 +288,28 @@ static bool ilk_fbc_is_active(struct
> drm_i915_private *dev_priv)
> static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
> {
> struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
> + struct intel_fbc_state_cache *cache = &dev_priv-
> >fbc.state_cache;
> u32 dpfc_ctl;
> int threshold = dev_priv->fbc.threshold;
>
> + /* Display WA #0529: skl, kbl, bxt but not for glk*/
> + if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) {
> + u32 chicken_misc4 = I915_READ(CHICKEN_MISC_4);
> +
> + if (i915_gem_object_get_tiling(cache->vma->obj)
params->vma->obj
> + != I915_TILING_X) {
> + int cfb_stride = DIV_ROUND_UP(cache-
> >plane.src_w,
> + (32 * threshold)) * 8;
> + params->fb.stride = cfb_stride;
Setting this here is too late. We need to do this in the same place as
we generate the other params.
> +
> + I915_WRITE(CHICKEN_MISC_4, chicken_misc4 |
> + FBC_STRIDE_OVERRIDE |
> cfb_stride);
This code is forgetting to mask the values it's going to replace.
> + } else {
> + I915_WRITE(CHICKEN_MISC_4, chicken_misc4 &
> + ~FBC_STRIDE_OVERRIDE);
> + }
> + }
> +
> dpfc_ctl = 0;
> if (IS_IVYBRIDGE(dev_priv))
> dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
