On Thu, Sep 07, 2017 at 07:45:20PM +0100, Chris Wilson wrote:
> We also see the delayed GTT write issue on i915g/i915gm, so let's
> presume that it is a universal problem for all !llc machines, and that we
> just haven't yet noticed on g33, gen4 and gen5 machines.
>
> v2: Use a register that exists on all platforms
>
> Testcase: igt/gem_mmap_gtt/coherency # i915gm
> References: https://bugs.freedesktop.org/show_bug.cgi?id=102577
> Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_gem.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 4dffebae5601..562c9510a7db 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -694,10 +694,10 @@ flush_write_domain(struct drm_i915_gem_object *obj,
> unsigned int flush_domains)
>
> switch (obj->base.write_domain) {
> case I915_GEM_DOMAIN_GTT:
> - if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) {
> + if (!HAS_LLC(dev_priv)) {
> intel_runtime_pm_get(dev_priv);
> spin_lock_irq(&dev_priv->uncore.lock);
> -
> POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
> +
> POSTING_READ_FW(RING_HEAD(dev_priv->engine[RCS]->mmio_base));
> spin_unlock_irq(&dev_priv->uncore.lock);
> intel_runtime_pm_put(dev_priv);
> }
> --
> 2.14.1
--
Ville Syrjälä
Intel OTC
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