On Wed, 2017-07-12 at 12:20 -0700, Rodrigo Vivi wrote:
> Continue on VPV PSR split with vfunc, let's also create one

Typo: s/VPV/VLV

> for enabling source.
> 
> Also since we are touching *_enable_source functions let's
> fix a comment with wrong name for vlv's one.
> 
> Cc: Daniel Vetter <daniel.vet...@ffwll.ch>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
> Cc: Jim Bride <jim.br...@linux.intel.com>
> Cc: Vathsala NAgaraju <vathsala.nagar...@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h  |  1 +
>  drivers/gpu/drm/i915/intel_psr.c | 13 ++++---------
>  2 files changed, 5 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 50b577b5e4d1..6a4d973e7fe9 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1146,6 +1146,7 @@ struct i915_psr {
>       bool colorimetry_support;
>       bool alpm;
>  
> +     void (*enable_source)(struct intel_dp *);
>       void (*disable_source)(struct intel_dp *);
>       void (*enable_sink)(struct intel_dp *);
>       void (*activate)(struct intel_dp *);
> diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> b/drivers/gpu/drm/i915/intel_psr.c
> index 73f7ba78f4d2..f4ceda6d6fd3 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -537,13 +537,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>  
>       dev_priv->psr.setup_vsc(intel_dp);
>       dev_priv->psr.enable_sink(intel_dp);
> -
> -     if (HAS_DDI(dev_priv)) {
> -             hsw_psr_enable_source(intel_dp);
> -     } else {
> -             vlv_psr_enable_source(intel_dp);
> -     }
> -
> +     dev_priv->psr.enable_source(intel_dp);
>       dev_priv->psr.enabled = intel_dp;
>  
>       if (INTEL_GEN(dev_priv) >= 9)
> @@ -770,8 +764,7 @@ static void intel_psr_exit(struct drm_i915_private 
> *dev_priv)
>                * directly once PSR State 4 that is active with single frame
>                * update can be skipped. PSR_state 5 that is PSR exit then
>                * Hardware is responsible to transition back to PSR_state 1
> -              * that is PSR inactive. Same state after
> -              * vlv_edp_psr_enable_source.
> +              * that is PSR inactive. Same state after vlv_psr_enable_source.
>                */
>               val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
>               I915_WRITE(VLV_PSRCTL(pipe), val);
> @@ -966,11 +959,13 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
>       mutex_init(&dev_priv->psr.lock);
>  
>       if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> +             dev_priv->psr.enable_source = vlv_psr_enable_source;
>               dev_priv->psr.disable_source = vlv_psr_disable;
>               dev_priv->psr.enable_sink = vlv_psr_enable_sink;
>               dev_priv->psr.activate = vlv_psr_activate;
>               dev_priv->psr.setup_vsc = vlv_psr_setup_vsc;
>       } else {
> +             dev_priv->psr.enable_source = hsw_psr_enable_source;
>               dev_priv->psr.disable_source = hsw_psr_disable;
>               dev_priv->psr.enable_sink = hsw_psr_enable_sink;
>               dev_priv->psr.activate = hsw_psr_activate;
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