From: Tom O'Rourke <Tom.O'rou...@intel.com>
i915.enable_slpc is used to override the default for slpc usage.
The expected values are -1=auto, 0=disabled [default], 1=enabled.
Sanitize i915.enable_slpc to either 0 or 1 based on HAS_SLPC() and
GuC load and submission options.
v1: Add early call to sanitize enable_slpc in intel_guc_ucode_init
Remove sanitize enable_slpc call before firmware version check
is performed. (ChrisW)
Version check is added in next patch and that will be done as
part of slpc_enable_sanitize function in the next patch. (Sagar)
Updated slpc option sanitize function call for platforms without
GuC support. This was caught by CI BAT.
v2: Changed parameter to dev_priv for HAS_SLPC macro. (David)
Code indentation based on checkpatch.
v3: Rebase.
v4: Moved sanitization of SLPC option post GuC load.
v5: Removed function intel_slpc_enabled. Planning to rely only on
kernel parameter. Moved sanitization prior to GuC load to use the
parameter during SLPC state setup during to GuC load. (Sagar)
v6: Commit message update. Rebase.
v7: Moved SLPC option sanitization to intel_uc_sanitize_options.
v8: Clearing SLPC option on GuC load failure. Change moved from later
patch. (Sagar)
Suggested-by: Paulo Zanoni <paulo.r.zan...@intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'rou...@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
drivers/gpu/drm/i915/i915_params.c | 5 +++++
drivers/gpu/drm/i915/i915_params.h | 1 +
drivers/gpu/drm/i915/intel_uc.c | 15 +++++++++++++++
3 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index d32d761..a14db53 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -43,6 +43,7 @@ struct i915_params i915 __read_mostly = {
.enable_dc = -1,
.enable_fbc = -1,
.enable_execlists = -1,
+ .enable_slpc = 0,
.enable_hangcheck = true,
.enable_ppgtt = -1,
.enable_psr = -1,
@@ -139,6 +140,10 @@ struct i915_params i915 __read_mostly = {
"Override execlists usage. "
"(-1=auto [default], 0=disabled, 1=enabled)");
+i915_param_named_unsafe(enable_slpc, int, 0400,
+ "Override single-loop-power-controller (slpc) usage. "
+ "(-1=auto, 0=disabled [default], 1=enabled)");
+
i915_param_named_unsafe(enable_psr, int, 0600,
"Enable PSR "
"(0=disabled, 1=enabled - link mode chosen per-platform, 2=force
link-standby mode, 3=force link-off mode) "
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index ac84470..d5c7bfb 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -41,6 +41,7 @@
func(int, enable_ppgtt); \
func(int, enable_execlists); \
func(int, enable_psr); \
+ func(int, enable_slpc); \
func(int, disable_power_well); \
func(int, enable_ips); \
func(int, invert_brightness); \
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index bb31243..eeec986 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -69,6 +69,7 @@ void intel_uc_sanitize_options(struct drm_i915_private
*dev_priv)
i915.enable_guc_loading = 0;
i915.enable_guc_submission = 0;
+ i915.enable_slpc = 0;
return;
}
@@ -92,6 +93,18 @@ void intel_uc_sanitize_options(struct drm_i915_private
*dev_priv)
/* A negative value means "use platform default" */
if (i915.enable_guc_submission < 0)
i915.enable_guc_submission = HAS_GUC_SCHED(dev_priv);
+
+ /* slpc requires hardware support and compatible firmware */
+ if (!HAS_SLPC(dev_priv))
+ i915.enable_slpc = 0;
+
+ /* slpc requires guc loaded */
+ if (!i915.enable_guc_loading)
+ i915.enable_slpc = 0;
+
+ /* slpc requires guc submission */
+ if (!i915.enable_guc_submission)
+ i915.enable_slpc = 0;
}
void intel_uc_init_early(struct drm_i915_private *dev_priv)
@@ -400,6 +413,8 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
i915.enable_guc_loading = 0;
DRM_NOTE("GuC firmware loading disabled\n");
+ i915.enable_slpc = 0;
+
return ret;
}
--
1.9.1
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