This Display Voltage and Frequency Switching Sequence
exist for a while, but now on CNL it got a separated doc in spec
and more attention since it is required to be called for more places.
So this series from Paulo and mostly from Mika addresses the changes
required specially for CNL.
Last patch in the series is optional and only aims to avoid code
duplication on SKL code. I know that this could be the first thing
in the series or squashed to Paulo's initial patch, but since this
is optional and I didn't wan't to disrupt and change the original
code from Paulo and Mika, I decided to do as the last patch on top
of their original work.
Thanks,
Rodrigo.
Kahola, Mika (3):
drm/i915/cnl: Expose DVFS change functions
drm/i915/cnl: DVFS for PLL enabling
drm/i915/cnl: DVFS for PLL disabling
Paulo Zanoni (1):
drm/i915/cnl: extract cnl_dvfs_{pre,post}_change
Rodrigo Vivi (1):
drm/i915: Extend DVFS function back to Skylake.
drivers/gpu/drm/i915/intel_cdclk.c | 50 ++++++++++++------------
drivers/gpu/drm/i915/intel_dpll_mgr.c | 71 +++++++++++++++++++++++++++--------
drivers/gpu/drm/i915/intel_drv.h | 2 +
3 files changed, 82 insertions(+), 41 deletions(-)
--
2.13.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
