On Tue, Nov 14, 2017 at 11:47:56AM -0800, Rodrigo Vivi wrote:
> Spec describe all values in MHz. We handle our
> clocks in KHz. This includes the best_dco_centrality that was
> forgot in the same unity as spec. Consequently we couldn't
> get a good divider for high frequenies. Hence HDMI 2.0 wasn't
> working.
>
> This patch also replaces the use of "* KHz(1)" with the values
> directly on KHz to avoid future confusion.
>
> Cc: Shashank Sharma <shashank.sha...@intel.com>
> Cc: Mika Kahola <mika.kah...@intel.com>
> Cc: Manasi Navare <manasi.d.nav...@intel.com>
> Cc: James Ausmus <james.aus...@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index fba969cbda37..53f650f56148 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2201,8 +2201,8 @@ cnl_ddi_calculate_wrpll(int clock,
> struct skl_wrpll_params *wrpll_params)
> {
> u32 afe_clock = clock * 5;
> - u32 dco_min = 7998 * KHz(1);
> - u32 dco_max = 10000 * KHz(1);
> + u32 dco_min = 7998000;
> + u32 dco_max = 10000000;
> u32 dco_mid = (dco_min + dco_max) / 2;
> static const int dividers[] = { 2, 4, 6, 8, 10, 12, 14, 16,
> 18, 20, 24, 28, 30, 32, 36, 40,
> @@ -2211,7 +2211,7 @@ cnl_ddi_calculate_wrpll(int clock,
> 84, 88, 90, 92, 96, 98, 100, 102,
> 3, 5, 7, 9, 15, 21 };
> u32 dco, best_dco = 0, dco_centrality = 0;
> - u32 best_dco_centrality = 999999;
> + u32 best_dco_centrality = 999999000;
UINT_MAX, -1, or ~0 maybe?
> int d, best_div = 0, pdiv = 0, qdiv = 0, kdiv = 0;
>
> for (d = 0; d < ARRAY_SIZE(dividers); d++) {
> --
> 2.13.6
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
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--
Ville Syrjälä
Intel OTC
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