From: Mahesh Kumar <mahesh1.ku...@intel.com>
Gen11/ICL onward ddb entry start/end mask is increased from 10 bits to
11 bits. This patch make changes to use proper mask for ICL+ during
hardware ddb value readout.
Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d4cd631377da..84a5b13fdee2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3860,10 +3860,18 @@ static unsigned int skl_cursor_allocation(int
num_active)
return 8;
}
-static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
+static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv,
+ struct skl_ddb_entry *entry, u32 reg)
{
- entry->start = reg & 0x3ff;
- entry->end = (reg >> 16) & 0x3ff;
+ uint16_t mask;
+
+ if (INTEL_GEN(dev_priv) >= 11)
+ mask = 0x7ff;
+ else
+ mask = 0x3ff;
+ entry->start = reg & mask;
+ entry->end = (reg >> 16) & mask;
+
if (entry->end)
entry->end += 1;
}
@@ -3894,7 +3902,9 @@ void skl_ddb_get_hw_state(struct drm_i915_private
*dev_priv,
else
val = I915_READ(CUR_BUF_CFG(pipe));
- skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id],
val);
+ skl_ddb_entry_init_from_hw(dev_priv,
+ &ddb->plane[pipe][plane_id],
+ val);
}
intel_display_power_put(dev_priv, power_domain);
--
2.14.3
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