We also need to extend this WA to Aux F. Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com> Cc: Lucas De Marchi <lucas.demar...@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com> Reviewed-by: Lucas De Marchi <lucas.demar...@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 4 +++- drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 44f46593172f..dda77443cb89 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8439,10 +8439,12 @@ enum skl_power_gate { #define _CNL_AUX_ANAOVRD1_B 0x162250 #define _CNL_AUX_ANAOVRD1_C 0x162210 #define _CNL_AUX_ANAOVRD1_D 0x1622D0 +#define _CNL_AUX_ANAOVRD1_F 0x162A90 #define CNL_AUX_ANAOVRD1(pw) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw), \ _CNL_AUX_ANAOVRD1_B, \ _CNL_AUX_ANAOVRD1_C, \ - _CNL_AUX_ANAOVRD1_D)) + _CNL_AUX_ANAOVRD1_D, \ + _CNL_AUX_ANAOVRD1_F)) #define CNL_AUX_ANAOVRD1_ENABLE (1<<16) #define CNL_AUX_ANAOVRD1_LDO_BYPASS (1<<23) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 93cc07998cc0..3526b563b8ec 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -395,7 +395,7 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv, /* Display WA #1178: cnl */ if (IS_CANNONLAKE(dev_priv) && (id == CNL_DISP_PW_AUX_B || id == CNL_DISP_PW_AUX_C || - id == CNL_DISP_PW_AUX_D)) { + id == CNL_DISP_PW_AUX_D || id == CNL_DISP_PW_AUX_F)) { val = I915_READ(CNL_AUX_ANAOVRD1(id)); val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS; I915_WRITE(CNL_AUX_ANAOVRD1(id), val); -- 2.13.6 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx