Write a PIPE_CONTROL with CS stall followed by 14 dwords of 0 in the
indirect context wa bb.
References: HSD#1939868
Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 51e61b04a555..fd7e7ffde570 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1366,6 +1366,25 @@ static u32 *gen9_init_indirectctx_bb(struct
intel_engine_cs *engine, u32 *batch)
return batch;
}
+static u32 *gen10_init_indirectctx_bb(struct intel_engine_cs *engine, u32
*batch)
+{
+ int i;
+
+ /* WaPipeControlBefore3DStateSamplePattern: cnl */
+ batch = gen8_emit_pipe_control(batch,
+ PIPE_CONTROL_CS_STALL,
+ 0);
+ for (i = 0; i < 8; i++)
+ *batch++ = MI_NOOP;
+
+ /* Pad to end of cacheline */
+ while ((unsigned long)batch % CACHELINE_BYTES)
+ *batch++ = MI_NOOP;
+
+ return batch;
+}
+
+
#define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE)
static int lrc_setup_wa_ctx(struct intel_engine_cs *engine)
@@ -1419,7 +1438,9 @@ static int intel_init_workaround_bb(struct
intel_engine_cs *engine)
switch (INTEL_GEN(engine->i915)) {
case 10:
- return 0;
+ wa_bb_fn[0] = gen10_init_indirectctx_bb;
+ wa_bb_fn[1] = NULL;
+ break;
case 9:
wa_bb_fn[0] = gen9_init_indirectctx_bb;
wa_bb_fn[1] = NULL;
--
2.14.3
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