Since when it got introduced with commit '555e38d27317
("drm/i915/cnl: DDI - PLL mapping")' the support for Port F
was wrong, because Port F bits are far from bits used
for A to E.
Since Port F is not used so far we don't need to propagate
Fixes back there.
v2: Reuse _SHIFT definition to avoid complicated duplication (DK).
Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
Cc: Lucas De Marchi <lucas.demar...@intel.com>
Cc: Manasi Navare <manasi.d.nav...@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 31e2fa602620..076a49107e02 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8844,10 +8844,12 @@ enum skl_power_gate {
* CNL Clocks
*/
#define DPCLKA_CFGCR0 _MMIO(0x6C200)
-#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port)+10))
-#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << ((port)*2))
-#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port)*2)
-#define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << ((port)*2))
+#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 :
\
+ (port)+10))
+#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \
+ (port)*2)
+#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 <<
DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
+#define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) <<
DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
/* CNL PLL */
#define DPLL0_ENABLE 0x46010
--
2.13.6
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