On Mon, Feb 12, 2018 at 12:33:57PM +0200, Jani Nikula wrote:
> On Thu, 08 Feb 2018, Imre Deak <imre.d...@intel.com> wrote:
> > On BXT/GLK GEN6_PCODE_READ_RC6VIDS fails with
> > MAILBOX_P24C_CC_ILLEGAL_CMD, so don't try to do the query on these
> > platforms. Do it only on SNB, IVB and HSW, where we use this command
> > anyway for RC6 enabling.
> >
> > Based on my tests the command also succeeds on all LLC platforms, but
> > it's not clear if it's really supported on those (it returns 0 aka 245mv
> > for all RC6 states everywhere except on SNB). BSpec lists the command as
> > supported on SKL+ (see P24C_PCODE_MAILBOX_INTERFACE) but that's clearly
> > incorrect, since on SKL/KBL the same command ID is used for
> > SKL_PCODE_LOAD_HDCP_KEYS. Since the command fails on BXT/GLK, the BSpec
> > command list is also incorrect for those platforms (see
> > P_CR_P24C_PCODE_MAILBOX_INTERFACE_0_2_0_GTTMMADR).
> >
> > I filed a request to update that info in Bspec, but for now let's
> > assume a minimal set of platforms where the command is supported.
> >
> > Reference: https://bugs.freedesktop.org/show_bug.cgi?id=103337
>
> If the patch fixes the bug, please use Bugzilla:.
>
> If the patch is related to the bug, please use References:.
It fixes a bug reported in that bug, but there are multiple issues
included in the report. So I suppose References: is the correct tag
then.
>
>
> BR,
> Jani.
>
>
> > Signed-off-by: Imre Deak <imre.d...@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_debugfs.c | 24 +++++++++++++++---------
> > 1 file changed, 15 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 2bdce9fea671..8f9045fae3cf 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -1484,9 +1484,12 @@ static int gen6_drpc_info(struct seq_file *m)
> > gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
> > }
> >
> > - mutex_lock(&dev_priv->pcu_lock);
> > - sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
> > - mutex_unlock(&dev_priv->pcu_lock);
> > + if (INTEL_GEN(dev_priv) <= 7) {
> > + mutex_lock(&dev_priv->pcu_lock);
> > + sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS,
> > + &rc6vids);
> > + mutex_unlock(&dev_priv->pcu_lock);
> > + }
> >
> > seq_printf(m, "RC1e Enabled: %s\n",
> > yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
> > @@ -1542,12 +1545,15 @@ static int gen6_drpc_info(struct seq_file *m)
> > print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
> > print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
> >
> > - seq_printf(m, "RC6 voltage: %dmV\n",
> > - GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
> > - seq_printf(m, "RC6+ voltage: %dmV\n",
> > - GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
> > - seq_printf(m, "RC6++ voltage: %dmV\n",
> > - GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
> > + if (INTEL_GEN(dev_priv) <= 7) {
> > + seq_printf(m, "RC6 voltage: %dmV\n",
> > + GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
> > + seq_printf(m, "RC6+ voltage: %dmV\n",
> > + GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
> > + seq_printf(m, "RC6++ voltage: %dmV\n",
> > + GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
> > + }
> > +
> > return i915_forcewake_domains(m, NULL);
> > }
>
> --
> Jani Nikula, Intel Open Source Technology Center
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