== Series Details ==
Series: Adding NV12 support (rev11)
URL : https://patchwork.freedesktop.org/series/28103/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
37fc44abdbe1 drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
-:65: CHECK: Alignment should match open parenthesis
#65: FILE: drivers/gpu/drm/i915/intel_pm.c:5049:
+skl_copy_ddb_for_pipe(struct skl_ddb_values *dst,
+ struct skl_ddb_values *src,
total: 0 errors, 0 warnings, 1 checks, 68 lines checked
c3472e45a098 drm/i915/skl+: refactor WM calculation for NV12
-:180: CHECK: Prefer kernel type 'u16' over 'uint16_t'
#180: FILE: drivers/gpu/drm/i915/intel_pm.c:4165:
+ uint16_t *minimum, uint16_t *uv_minimum)
-:198: CHECK: Prefer kernel type 'u16' over 'uint16_t'
#198: FILE: drivers/gpu/drm/i915/intel_pm.c:4198:
+ uint16_t uv_minimum[I915_MAX_PLANES] = {};
-:247: CHECK: Prefer kernel type 'u16' over 'uint16_t'
#247: FILE: drivers/gpu/drm/i915/intel_pm.c:4262:
+ uint16_t plane_blocks, uv_plane_blocks;
total: 0 errors, 0 warnings, 3 checks, 293 lines checked
f4e98e5d8417 drm/i915/skl+: add NV12 in skl_format_to_fourcc
b8121b942b13 drm/i915/skl+: support verification of DDB HW state for NV12
f2afa54b0be2 drm/i915/skl+: NV12 related changes for WM
238d40b3ef30 drm/i915/skl+: pass skl_wm_level struct to wm compute func
080ae278ef65 drm/i915/skl+: make sure higher latency level has higher wm value
a82f7ae342b3 drm/i915/skl+: nv12 workaround disable WM level 1-7
-:34: CHECK: Unnecessary parentheses around 'level >= 1'
#34: FILE: drivers/gpu/drm/i915/intel_pm.c:4664:
+ if (wp->is_planar && (level >= 1) &&
+ (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
+ IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))) {
-:35: CHECK: Alignment should match open parenthesis
#35: FILE: drivers/gpu/drm/i915/intel_pm.c:4665:
+ if (wp->is_planar && (level >= 1) &&
+ (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
total: 0 errors, 0 warnings, 2 checks, 17 lines checked
f708ecd83f9a drm/i915/skl: split skl_compute_ddb function
-:113: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#113: FILE: drivers/gpu/drm/i915/intel_pm.c:5144:
+ uint32_t realloc_pipes = pipes_modified(state);
-:132: CHECK: spaces preferred around that '*' (ctx:ExV)
#132: FILE: drivers/gpu/drm/i915/intel_pm.c:5163:
+ *changed = true;
^
total: 0 errors, 0 warnings, 2 checks, 194 lines checked
9d1fa6c655c9 drm/i915: Set scaler mode for NV12
-:55: CHECK: Prefer using the BIT macro
#55: FILE: drivers/gpu/drm/i915/i915_reg.h:6735:
+#define PS_SCALER_MODE_PLANAR (1 << 29)
total: 0 errors, 0 warnings, 1 checks, 21 lines checked
0ae0b2729b35 drm/i915: Update format_is_yuv() to include NV12
d1c743d06870 drm/i915: Upscale scaler max scale for NV12
-:146: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#146: FILE: drivers/gpu/drm/i915/intel_display.c:12836:
+ uint32_t pixel_format = 0;
total: 0 errors, 0 warnings, 1 checks, 119 lines checked
62adeaa74a33 drm/i915: Add NV12 as supported format for primary plane
-:57: CHECK: Unnecessary parentheses around 'pipe == PIPE_C'
#57: FILE: drivers/gpu/drm/i915/intel_display.c:13259:
+ if ((INTEL_GEN(dev_priv) == 9 && (pipe == PIPE_C)) &&
+ !IS_GEMINILAKE(dev_priv))
-:58: CHECK: Alignment should match open parenthesis
#58: FILE: drivers/gpu/drm/i915/intel_display.c:13260:
+ if ((INTEL_GEN(dev_priv) == 9 && (pipe == PIPE_C)) &&
+ !IS_GEMINILAKE(dev_priv))
total: 0 errors, 0 warnings, 2 checks, 17 lines checked
afe83893650a drm/i915: Add NV12 as supported format for sprite plane
-:71: CHECK: Alignment should match open parenthesis
#71: FILE: drivers/gpu/drm/i915/intel_sprite.c:1374:
+ if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv) &&
+ (plane != 0 || pipe == PIPE_C)) ||
total: 0 errors, 0 warnings, 1 checks, 19 lines checked
7558353b0351 drm/i915: Add NV12 support to intel_framebuffer_init
-:61: WARNING: line over 80 characters
#61: FILE: drivers/gpu/drm/i915/intel_display.c:14069:
+
drm_get_format_name(mode_cmd->pixel_format,
-:62: CHECK: Alignment should match open parenthesis
#62: FILE: drivers/gpu/drm/i915/intel_display.c:14070:
+
drm_get_format_name(mode_cmd->pixel_format,
+ &format_name));
total: 0 errors, 1 warnings, 1 checks, 14 lines checked
f716c88bee62 drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
-:21: CHECK: Prefer using the BIT macro
#21: FILE: drivers/gpu/drm/i915/i915_reg.h:6458:
+#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 (1 << 17)
total: 0 errors, 0 warnings, 1 checks, 20 lines checked
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