On Tue, Oct 23, 2012 at 4:57 PM, Ben Widawsky <b...@bwidawsk.net> wrote: > Actually, after we introduce the FLSH_CNTL patch from Jesse/me later in the > series, I think we just want a POSTING_READ on that register. It is > technically "required" by our desire to some day WC the registers, and > should synchronize everything else for us. > > After a quick read of memory_barriers.txt (again), I think mmiowb is > actually what we might want in addition to the POSTING_READ I'd add.
Imo we have special rules for the igd, since clearly not all registers in our 4mb mmio window are equal. So I'd prefer the keep the readback of the last pte write (to ensure those are flushed out) and maybe also add a readback of the gfx_flsh_cntl reg (like I've seen in some internal vlv tree). Just to be paranoid. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
