[Intel-gfx] [PATCH 6/6] drm/i915/psr/hsw+: Enable CRC check in the static frame on the sink side

[José Roberto de Souza]

Sink can be configured to calculate the CRC over the static frame and
compare with the CRC calculated and transmited in the VSC SDP by
source, if there is a mismatch sink will do a short pulse in HPD
and set DP_PSR_LINK_CRC_ERROR on DP_PSR_ERROR_STATUS.

Signed-off-by: José Roberto de Souza <jose.so...@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  1 +
 drivers/gpu/drm/i915/intel_psr.c | 15 +++++++--------
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f36e839b4b4f..ca68eef8d90a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4122,6 +4122,7 @@ enum {
 #define   EDP_PSR_SKIP_AUX_EXIT                        (1<<12)
 #define   EDP_PSR_TP1_TP2_SEL                  (0<<11)
 #define   EDP_PSR_TP1_TP3_SEL                  (1<<11)
+#define   EDP_PSR_CRC_ENABLE                   (1<<10)
 #define   EDP_PSR_TP2_TP3_TIME_500us           (0<<8)
 #define   EDP_PSR_TP2_TP3_TIME_100us           (1<<8)
 #define   EDP_PSR_TP2_TP3_TIME_2500us          (2<<8)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 4e73edf1ea5b..f6af8e8039c9 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -160,6 +160,7 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
        enum port port = dig_port->base.port;
        u32 aux_ctl;
        int i;
+       uint8_t val;
 
        BUILD_BUG_ON(sizeof(aux_msg) > 20);
 
@@ -175,12 +176,10 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
                drm_dp_dpcd_writeb(&intel_dp->aux,
                                DP_RECEIVER_ALPM_CONFIG,
                                DP_ALPM_ENABLE);
+       val = DP_PSR_ENABLE | DP_PSR_CRC_VERIFICATION;
        if (dev_priv->psr.link_standby)
-               drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
-                                  DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
-       else
-               drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
-                                  DP_PSR_ENABLE);
+               val |= DP_PSR_MAIN_LINK_ACTIVE;
+       drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val);
 
        aux_ctl_reg = psr_aux_ctl_reg(dev_priv, port);
 
@@ -241,7 +240,7 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
         * with the 5 or 6 idle patterns.
         */
        uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
-       uint32_t val = EDP_PSR_ENABLE;
+       uint32_t val = EDP_PSR_ENABLE | EDP_PSR_CRC_ENABLE;
 
        val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
        val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
@@ -1015,12 +1014,12 @@ void intel_psr_hpd_short_pulse_handle(struct intel_dp 
*intel_dp)
                goto dpcd_read_error;
        }
 
-       if (val & DP_PSR_RFB_STORAGE_ERROR)
+       if (val & (DP_PSR_RFB_STORAGE_ERROR | DP_PSR_LINK_CRC_ERROR))
                dev_priv->psr.exit(intel_dp, false);
        /* clear status register */
        drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, val);
 
-       /* TODO: handle other PSR/PSR2 errors */
+       /* TODO: handle PSR2 errors */
 dpcd_read_error:
        intel_psr_active_schedule(psr, PSR_ACTIVE_DELAY_MSEC);
 out:
-- 
2.16.2

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