Quoting Michal Wajdeczko (2018-03-08 21:00:35) > Instead of dancing around uC on reset/suspend/resume scenarios, > explicitly sanitize uC when we sanitize GEM to force uC reload > and start from known beginning. > > Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> > Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> > Cc: Chris Wilson <ch...@chris-wilson.co.uk> > Cc: Michel Thierry <michel.thie...@intel.com>
Lgtm, Reviewed-by: Chris Wilson <ch...@chris-wilson.co.uk> Second opinions are welcome. > --- > drivers/gpu/drm/i915/i915_gem.c | 2 ++ > drivers/gpu/drm/i915/intel_guc.h | 6 ++++++ > drivers/gpu/drm/i915/intel_huc.h | 6 ++++++ > drivers/gpu/drm/i915/intel_uc.c | 18 ++++++++++++++++++ > drivers/gpu/drm/i915/intel_uc.h | 1 + > drivers/gpu/drm/i915/intel_uc_fw.h | 6 ++++++ > 6 files changed, 39 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index ab88ca5..49c81ae 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -4892,6 +4892,8 @@ void i915_gem_sanitize(struct drm_i915_private *i915) > */ > if (INTEL_GEN(i915) >= 5 && intel_has_gpu_reset(i915)) > WARN_ON(intel_gpu_reset(i915, ALL_ENGINES)); I think we can say that our reset works for gen3+ well enough to use everywhere. (Certainly gen3/gen4 are no worse than gen5!) Future task for the brave. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx