Hi Matt, Minor commit message nits.
On Thu, Mar 08, 2018 at 05:17:38PM -0800, matthew.s.atw...@intel.com wrote: > From: Matt Atwood <matthew.s.atw...@intel.com> > > Previously it was assumed that eDP panels would advertise the lowest link > rate required for their singular mode to function. With the introduction > of more advanced features there are advantages to a panel advertising a > higher rate then s/then/than > it needs for a its given mode. Don't need "its" here. > For panels that did, the > driver previously used a higher rate then necessary for that mode. > s/then/than > Signed-off-by: Matt Atwood <matthew.s.atw...@intel.com> Tested-by: Benson Leung <ble...@chromium.org> Tested this on a panel and system with the following source and sink rates: [ 1.623225] [drm:intel_dp_print_rates] source rates: 162000, 216000, 270000, 324000, 432000, 540000 [ 1.623230] [drm:intel_dp_print_rates] sink rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000 [ 1.623234] [drm:intel_dp_print_rates] common rates: 162000, 216000, 270000, 324000, 432000, 540000 Prior to this patch, the driver would pick and train at 540000: [ 2.865653] [drm:intel_dp_start_link_train] [CONNECTOR:76:eDP-1] Link Training Passed at Link Rate = 540000, Lane count = 4 After this patch, the driver picks and trains at 324000, which is enough for the panel's native mode: [ 5.359499] [drm:intel_dp_start_link_train] [CONNECTOR:76:eDP-1] Link Training Passed at Link Rate = 324000, Lane count = 4 Thanks! Benson -- Benson Leung Staff Software Engineer Chrome OS Kernel Google Inc. ble...@google.com Chromium OS Project ble...@chromium.org
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