On 2018-03-19 14:53, Joonas Lahtinen wrote:
+ Dave, as FYI
Quoting Tomasz Lis (2018-03-19 14:37:34)
The OpenCL driver develpers requested a functionality to control cache
coherency at data port level. Keeping the coherency at that level is disabled
by default due to its performance costs. OpenCL driver is planning to
enable it for a small subset of submissions, when such functionality is
required.
Can you please link to the corresponding OpenCL driver changes? I'm
assuming this relates to the new-driver-to-be-adopted, instead of
Beignet?
It is for the new driver; I will ask the OCL developers to provide a link.
How is the story/schedule looking for adopting the new driver to
distros?
I guess that's another question for OCL guys, I don't know.
Seeing the userspace counterpart and tests will help in assessing the
suggested changes.
Regards, Joonas
I prepared an IGT test for that, I will send it to a proper mailing list
soon.
-Tomasz
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