On Thu, Mar 22, 2018 at 02:48:37PM -0700, José Roberto de Souza wrote: > To comply with eDP1.4a this bit should be set when enabling PSR2. > > Signed-off-by: José Roberto de Souza <jose.so...@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.v...@intel.com> > --- > include/drm/drm_dp_helper.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > index 62903bae0221..0bac0c7d0dec 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -478,6 +478,7 @@ > # define DP_PSR_FRAME_CAPTURE (1 << 3) > # define DP_PSR_SELECTIVE_UPDATE (1 << 4) > # define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5) > +# define DP_PSR_ENABLE_PSR2 (1 << 6) /* eDP 1.4a */ > > #define DP_ADAPTER_CTRL 0x1a0 > # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0) > -- > 2.16.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
