On Fri, 2018-04-06 at 16:36 -0700, José Roberto de Souza wrote:
> On Mon, 2018-04-02 at 15:38 -0700, Pandiyan, Dhinakaran wrote:
> > On Mon, 2018-04-02 at 13:51 -0700, José Roberto de Souza wrote:
> > > IGT tests could be improved with sink status, knowing for sure
> > > that
> > > hardware have activate or exit PSR.
> > >
> > > Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
> >
> >
> > Please don't merge this patch yet. While the patch itself is
> > correct,
> > testing it brings up an interesting problem.
> >
> > Printing the sink_status() leads to power_get(aux_domain) which
> > wakes
> > up
> > the display engine from DC5/6. This results in a HW triggered PSR
> > exit,
> > effectively altering the state that we are trying to read. I would
> > like
> > to understand the problem fully before merging the patch.
>
> In my tests(PSR1 only) with DMC loaded, I can see HW trigerring PSR
> exit when reading i915_edp_psr_status with or without this patch, the
> event that caused is 'SRD Mask Reg Write'.
> After masking EDP_PSR_DEBUG_MASK_DISP_REG_WRITE in EDP_PSR_DEBUG it
> do
> not happens with or without this patch.
>
> Masking this event did not bring more IGT errors than we have now,
> what
> do you think Dhinakaran? Should we mask it?
Another information missed:
When doing a dpcd(I did not look at what exacly is causing it)
transaction it is causing the HW to be awaken from DC6 with or without
masking EDP_PSR_DEBUG_MASK_DISP_REG_WRITE but when masking it do not
cause a PSR exit.
Reading i915_sr_status also cause HW to be awaken from DC6.
>
> >
> >
> > > Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> > > Signed-off-by: José Roberto de Souza <jose.so...@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_debugfs.c | 29
> > > +++++++++++++++++++++++++++++
> > > 1 file changed, 29 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > > b/drivers/gpu/drm/i915/i915_debugfs.c
> > > index 1dba2c451255..c9ac946b62c9 100644
> > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > @@ -2603,6 +2603,26 @@ static const char *psr2_live_status(u32
> > > val)
> > > return "unknown";
> > > }
> > >
> > > +static const char *psr_sink_status(u8 val)
> > > +{
> > > + static const char * const sink_status[] = {
> > > + "inactive",
> > > + "transition to active, capture and display",
> > > + "active, display from RFB",
> > > + "active, capture and display on sink device
> > > timings",
> > > + "transition to inactive, capture and display,
> > > timing re-sync",
> > > + "reserved",
> > > + "reserved",
> > > + "sink internal error"
> > > + };
> > > +
> > > + val &= DP_PSR_SINK_STATE_MASK;
> > > + if (val < ARRAY_SIZE(sink_status))
> > > + return sink_status[val];
> > > +
> > > + return "unknown";
> > > +}
> > > +
> > > static int i915_edp_psr_status(struct seq_file *m, void *data)
> > > {
> > > struct drm_i915_private *dev_priv = node_to_i915(m-
> > > > private);
> > >
> > > @@ -2684,6 +2704,15 @@ static int i915_edp_psr_status(struct
> > > seq_file *m, void *data)
> > > seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
> > > psr2, psr2_live_status(psr2));
> > > }
> > > +
> > > + if (dev_priv->psr.enabled) {
> > > + struct drm_dp_aux *aux = &dev_priv->psr.enabled-
> > > > aux;
> > >
> > > + u8 val;
> > > +
> > > + if (drm_dp_dpcd_readb(aux, DP_PSR_STATUS, &val)
> > > ==
> > > 1)
> > > + seq_printf(m, "Sink PSR status: 0x%x
> > > [%s]\n", val,
> > > + psr_sink_status(val));
> > > + }
> > > mutex_unlock(&dev_priv->psr.lock);
> > >
> > > intel_runtime_pm_put(dev_priv);
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
