== Series Details ==
Series: More ICL display patches (rev2)
URL : https://patchwork.freedesktop.org/series/43546/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
127450a17db7 drm/i915/icl: Extend AUX F interrupts to ICL
531f7327f015 drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC
f399dccd8cc6 drm/i915/icl: introduce tc_port
3f0e2981505d drm/i915/icl: Support for TC North Display interrupts
e4ec5bf09dc4 drm/i915/icp: Add Interrupt Support
6cb5cbdd40c5 drm/i915/ICL: Add register definition for DFLEXDPMLE
d33c632e9ea9 drm/i915/icl: Add DDI HDMI level selection for ICL
d58f0e17059b drm/i915/icl: Map VBT DDC Pin to BSpec DDC Pin
f9905e6229bc drm/i915/icl: Add Icelake PCH detection
1da0c5f49ffc drm/i915/icl: add icelake_get_ddi_pll()
ba91e7a19262 drm/i915/icl: Get DDI clock for ICL based on PLLs.
4a59b2d6c399 drm/i915/icl: Calculate link clock using the new registers
41d365245a0d drm/i915/icl: unconditionally init DDI for every port
e30520c96c42 drm/i915/icl: start adding the TBT pll
-:162: CHECK:LINE_SPACING: Please use a blank line after
function/struct/union/enum declarations
#162: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.h:137:
};
+#define I915_NUM_PLLS 7
total: 0 errors, 0 warnings, 1 checks, 129 lines checked
4d717c17a206 drm/i915/icl: compute the TBT PLL registers
-:18: CHECK:CAMELCASE: Avoid CamelCase: <icl_tbt_pll_24MHz_values>
#18: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2455:
+static const struct skl_wrpll_params icl_tbt_pll_24MHz_values = {
-:23: CHECK:CAMELCASE: Avoid CamelCase: <icl_tbt_pll_19_2MHz_values>
#23: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2460:
+static const struct skl_wrpll_params icl_tbt_pll_19_2MHz_values = {
total: 0 errors, 0 warnings, 2 checks, 51 lines checked
839e6e916ef0 drm/i915/icl: Handle hotplug interrupts for DP over TBT
f9457e7eaac0 drm/i915/icl: Add 10-bit support for hdmi
d39f683cc31c drm/i915/icl: implement icl_digital_port_connected()
44c232d87e62 drm/i915/icl: store the port type for TC ports
e9916912b1a7 drm/i915/icl: implement the tc/legacy HPD {dis, }connect flow for
DP
e737bd4f64f3 drm/i915/icl: implement the legacy HPD {dis, }connect flow for HDMI
cd9cf1051643 drm/i915/icl: Update FIA supported lane count for hpd.
b46919848803 drm/i915/icl: program MG_DP_MODE
c7b5ae16c069 drm/i915/icl: toggle PHY clock gating around link training
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