Patches needed to change cdclk to 2*BCLK before accessing HDA Codec. Ville Syrjälä (2): drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled drm/i915: Shut off PW2 when changing cdclk on glk
drivers/gpu/drm/i915/i915_drv.h | 3 ++ drivers/gpu/drm/i915/i915_reg.h | 4 ++ drivers/gpu/drm/i915/intel_audio.c | 67 +++++++++++++++++++++++++++++++-- drivers/gpu/drm/i915/intel_cdclk.c | 43 +++++++++++---------- drivers/gpu/drm/i915/intel_display.c | 7 +++- drivers/gpu/drm/i915/intel_drv.h | 7 ++++ drivers/gpu/drm/i915/intel_runtime_pm.c | 34 +++++++++++++++++ 7 files changed, 140 insertions(+), 25 deletions(-) -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
