Quoting Lis, Tomasz (2018-07-20 15:41:33) > > > On 2018-07-20 12:19, Chris Wilson wrote: > > Not all chipsets have an internal buffer delaying the visibility of > > writes via the GGTT being visible by other physical paths, but we use a > > very heavy workaround for all. We only need to apply that workarounds to > > the chipsets we know suffer from the delay and the resulting coherency > > issue. > > > > Similarly, the same inconsistent coherency fouls up our ABI promise that > > a write into a mmap_gtt is immediately visible to others. Since the HW > > has made that a lie, let userspace know when that contract is broken. > > (Not that userspace would want to use mmap_gtt on those chipsets for > > other performance reasons...) > > > > Testcase: igt/drv_selftest/live_coherency > > Testcase: igt/gem_mmap_gtt/coherency > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100587 > > Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> > > Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> > Is there any mention of this bug/feature in bspec? Would be nice to have > a reference.
I know that some HW bod has come across it, as they recommended the same for ordering mem access between us using the GTT for iomaps and GuC submission. All I know is the background chatter... We don't seem to have a named w/a; iirc it was just concluded that was the way it was meant to work ;) -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
