[Intel-gfx] [PATCH 12/20] drm/i915: Unset reset pch handshake when PCH is not present in one place

[José Roberto de Souza]

Right now RESET_PCH_HANDSHAKE_ENABLE is enabled all the times inside
of intel_power_domains_init_hw() and if PCH is NOP it is unsed in
i915_gem_init_hw().
So making skl_pch_reset_handshake() handle both cases and calling
it for the missing gens in intel_power_domains_init_hw().
Ivybridge have a different register and bits but with the same
objective so moving it too.

Signed-off-by: José Roberto de Souza <jose.so...@intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c         | 12 ------------
 drivers/gpu/drm/i915/intel_runtime_pm.c | 16 +++++++++++++++-
 2 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 71502512ac1f..49151d79e3b1 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5283,18 +5283,6 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
                I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
                           LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
 
-       if (HAS_PCH_NOP(dev_priv)) {
-               if (IS_IVYBRIDGE(dev_priv)) {
-                       u32 temp = I915_READ(GEN7_MSG_CTL);
-                       temp &= ~(WAIT_FOR_PCH_FLR_ACK | 
WAIT_FOR_PCH_RESET_ACK);
-                       I915_WRITE(GEN7_MSG_CTL, temp);
-               } else if (INTEL_GEN(dev_priv) >= 7) {
-                       u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
-                       temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
-                       I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
-               }
-       }
-
        intel_gt_workarounds_apply(dev_priv);
 
        i915_gem_init_swizzling(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 97178d512852..43d7f9071ff4 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3265,11 +3265,16 @@ static void icl_mbus_init(struct drm_i915_private 
*dev_priv)
        I915_WRITE(MBUS_ABOX_CTL, val);
 }
 
+/* Actually it is hsw+ but until skl it was not required to set it */
 static void skl_pch_reset_handshake(struct drm_i915_private *dev_priv)
 {
        u32 val = I915_READ(HSW_NDE_RSTWRN_OPT);
 
-       val |= RESET_PCH_HANDSHAKE_ENABLE;
+       if (HAS_PCH_NOP(dev_priv))
+               val &= ~RESET_PCH_HANDSHAKE_ENABLE;
+       else
+               val |= RESET_PCH_HANDSHAKE_ENABLE;
+
        I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
 }
 
@@ -3773,6 +3778,15 @@ void intel_power_domains_init_hw(struct drm_i915_private 
*dev_priv, bool resume)
                mutex_lock(&power_domains->lock);
                vlv_cmnlane_wa(dev_priv);
                mutex_unlock(&power_domains->lock);
+       } else if (IS_IVYBRIDGE(dev_priv)) {
+               if (HAS_PCH_NOP(dev_priv)) {
+                       u32 val = I915_READ(GEN7_MSG_CTL);
+
+                       val &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
+                       I915_WRITE(GEN7_MSG_CTL, val);
+               }
+       } else if (INTEL_GEN(dev_priv) >= 7) {
+               skl_pch_reset_handshake(dev_priv);
        }
 
        /* For now, we need the power well to be always enabled. */
-- 
2.18.0

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