[Intel-gfx] [PATCH 16/21] drm/i915/guc: New engine-reset-complete message

[Michal Wajdeczko]

GuC sends ENGINE_RESET_COMPLETE message as an follow-up answer
to earlier ENGINE_RESET request from the host. Once this message
is received, clear engine reset flag to unblock our reset process.

Credits-to: Michel Thierry <michel.thie...@intel.com>
Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Michel Thierry <michel.thie...@intel.com>
Cc: Vinay Belgaumkar <vinay.belgaum...@intel.com>
Cc: Michal Winiarski <michal.winiar...@intel.com>
Cc: Tomasz Lis <tomasz....@intel.com>
---
 drivers/gpu/drm/i915/intel_guc.c      | 29 +++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_guc_fwif.h |  3 ++-
 2 files changed, 31 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index da61115..9a177ff 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -27,6 +27,9 @@
 #include "intel_guc_submission.h"
 #include "i915_drv.h"
 
+static void guc_handle_engine_reset_completed(struct intel_guc *guc,
+                                             const u32 engine_class);
+
 static void gen8_guc_raise_irq(struct intel_guc *guc)
 {
        struct drm_i915_private *dev_priv = guc_to_i915(guc);
@@ -528,6 +531,12 @@ int intel_guc_to_host_process_recv_msg(struct intel_guc 
*guc,
                   INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED))
                intel_guc_log_handle_flush_event(&guc->log);
 
+       if (msg & INTEL_GUC_RECV_MSG_ENGINE_RESET_COMPLETE) {
+               if (len != 3)
+                       return -EPROTO;
+               guc_handle_engine_reset_completed(guc, payload[1]);
+       }
+
        return 0;
 }
 
@@ -588,6 +597,7 @@ int intel_guc_suspend(struct intel_guc *guc)
 {
        GEM_BUG_ON(guc_class >= GUC_MAX_ENGINE_CLASSES);
        bitmap32_set_bit(&guc->engine_class_under_reset, guc_class);
+       intel_guc_enable_msg(guc, INTEL_GUC_RECV_MSG_ENGINE_RESET_COMPLETE);
 }
 
 static inline void
@@ -595,6 +605,7 @@ int intel_guc_suspend(struct intel_guc *guc)
 {
        GEM_BUG_ON(guc_class >= GUC_MAX_ENGINE_CLASSES);
        bitmap32_clear_bit(&guc->engine_class_under_reset, guc_class);
+       intel_guc_disable_msg(guc, INTEL_GUC_RECV_MSG_ENGINE_RESET_COMPLETE);
 }
 
 static inline bool
@@ -659,6 +670,24 @@ int intel_guc_reset_engine(struct intel_guc *guc,
        return ret;
 }
 
+/*
+ * GuC notifies host that reset engine has completed.
+ * This message should only be received after a request-reset h2g,
+ * so check that and clear the engine_class_under_reset flag.
+ */
+static void guc_handle_engine_reset_completed(struct intel_guc *guc,
+                                             const u32 engine_class)
+{
+       if (engine_class >= GUC_MAX_ENGINE_CLASSES ||
+           !guc_is_class_under_reset(guc, engine_class)) {
+               DRM_WARN("Unexpected reset-complete for engine class: %d",
+                        engine_class);
+               return;
+       }
+
+       guc_clear_class_under_reset(guc, engine_class);
+}
+
 /**
  * intel_guc_resume() - notify GuC resuming from suspend state
  * @guc:       the guc
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 156db08..1958581 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -757,7 +757,8 @@ enum intel_guc_response_status {
 /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
 enum intel_guc_recv_message {
        INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
-       INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = BIT(3)
+       INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = BIT(3),
+       INTEL_GUC_RECV_MSG_ENGINE_RESET_COMPLETE = BIT(25),
 };
 
 #endif
-- 
1.9.1

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