On Fri, Sep 14, 2018 at 12:24:14PM +0530, Vandita Kulkarni wrote:
> From: Madhav Chauhan <madhav.chau...@intel.com>
>
> This patch calculate various DPLL dividers and
> parameters for DSI encoder and adjust AFE clock
> for DSI. For DSI, 8x clock is AFE clock.
>
> v2: Extend haswell_crtc_compute_clock() for Gen11 DSI
> v3: Rebase
>
> Signed-off-by: Madhav Chauhan <madhav.chau...@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulka...@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 4 +++-
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 7 ++++++-
> 2 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 6928dcc..1a44c5e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9238,10 +9238,12 @@ void hsw_disable_pc8(struct drm_i915_private
> *dev_priv)
> static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
> struct intel_crtc_state *crtc_state)
> {
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_atomic_state *state =
> to_intel_atomic_state(crtc_state->base.state);
>
> - if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
> + if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
> + IS_ICELAKE(dev_priv)) {
> struct intel_encoder *encoder =
> intel_get_crtc_new_encoder(state, crtc_state);
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 36ed155..5175e44 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -22,6 +22,7 @@
> */
>
> #include "intel_drv.h"
> +#include "intel_dsi.h"
>
> /**
> * DOC: Display PLLs
> @@ -2532,7 +2533,11 @@ static bool icl_calc_dpll_state(struct
> intel_crtc_state *crtc_state,
> ret = icl_calc_tbt_pll(dev_priv, clock, &pll_params);
> else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> ret = cnl_ddi_calculate_wrpll(clock, dev_priv, &pll_params);
> - else
> + else if (encoder->type == INTEL_OUTPUT_DSI) {
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + ret = cnl_ddi_calculate_wrpll(intel_dsi->bitrate_khz/5,
Missing port_clock=whatever in compute config?
> + dev_priv, &pll_params);
> + } else
> ret = icl_calc_dp_combo_pll(dev_priv, clock, &pll_params);
>
> if (!ret)
> --
> 1.9.1
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
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