Quoting Radhakrishna Sripada (2018-09-28 17:47:32)
> Gen11 Display suports 32 planes in total. Enable the new format in context
> status to be used and expanded to 32 planes.
>
> Cc: Oscar Mateo Lozano <oscar.ma...@intel.com>
> Cc: Michel Thierry <michel.thie...@intel.com>
> Cc: James Ausmus <james.aus...@intel.com>
> Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.srip...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_workarounds.c | 4 ++++
> 2 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 27e650fe591b..263de5b54d69 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2573,6 +2573,7 @@ enum i915_power_well_id {
> /* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
> #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
> #define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
> +#define GEN11_ENABLE_32_PLANE_MODE (1 << 7)
>
> /* WaClearTdlStateAckDirtyBits */
> #define GEN8_STATE_ACK _MMIO(0x20F0)
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
> b/drivers/gpu/drm/i915/intel_workarounds.c
> index 4bcdeaf8d98f..ba4009b4ad2c 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -905,6 +905,10 @@ static void icl_gt_workarounds_apply(struct
> drm_i915_private *dev_priv)
> I915_WRITE(GAMT_CHKN_BIT_REG,
> I915_READ(GAMT_CHKN_BIT_REG) |
> GAMT_CHKN_DISABLE_L3_COH_PIPE);
> +
> + /* WaEnable32PlaneMode:icl */
> + I915_WRITE(GEN9_CSFE_CHICKEN1_RCS,
> + _MASKED_BIT_ENABLE(GEN11_ENABLE_32_PLANE_MODE));
gt_wa for display? Odd choice of location.
-Chris
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