On Fri, 2018-11-02 at 20:07 +0200, Imre Deak wrote: > BSpec says to clear the comp init HW flag too during combo PHY > uninit, > so do that. The lack of this could badly interact with the PHY reinit > after a DC6/9 transition at least, where (after a follow-up patch > fixing > the init code) we'd skip the initialization incorrectly due to this > flag > being set. > > BSpec: 21257 > Cc: Paulo Zanoni <paulo.r.zan...@intel.com> > Cc: Ville Syrjälä <ville.syrj...@linux.intel.com> > Cc: José Roberto de Souza <jose.so...@intel.com> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.c > Signed-off-by: Imre Deak <imre.d...@intel.com> > --- > drivers/gpu/drm/i915/intel_runtime_pm.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c > b/drivers/gpu/drm/i915/intel_runtime_pm.c > index 6c453366cd24..a7eea8423580 100644 > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > @@ -3668,6 +3668,10 @@ void icl_display_core_uninit(struct > drm_i915_private *dev_priv) > val = I915_READ(ICL_PHY_MISC(port)); > val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; > I915_WRITE(ICL_PHY_MISC(port), val); > + > + val = I915_READ(ICL_PORT_COMP_DW0(port)); > + val &= ~COMP_INIT; > + I915_WRITE(ICL_PORT_COMP_DW0(port), val);
As DDIA PHY is the master maybe would be more safe clear it by last? Other than that: Reviewed-by: José Roberto de Souza <jose.so...@intel.com> > } > } > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
