On Fri, 2018-11-02 at 21:26 +0200, Imre Deak wrote:
> The MG PHY clock gating needs to be configured for Type C
> static/fixed/legacy HDMI ports the same way it's configured for Type
> C
> static/fixed/legacy and aternate mode DP ports, fix this.
>
Reviewed-by: José Roberto de Souza <jose.so...@intel.com>
> Bspec: 4232, 21735
> Cc: Vandita Kulkarni <vandita.kulka...@intel.com>
> Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
> Cc: Maarten Lankhorst <maarten.lankho...@linux.intel.com>
> Cc: Manasi Navare <manasi.d.nav...@intel.com>
> Signed-off-by: Imre Deak <imre.d...@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 70
> ++++++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_dp.c | 66 ------------------------------
> -------
> drivers/gpu/drm/i915/intel_drv.h | 2 --
> 3 files changed, 70 insertions(+), 68 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 3eea987e909b..cb06058179fd 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2914,6 +2914,72 @@ static void intel_ddi_clk_disable(struct
> intel_encoder *encoder)
> }
> }
>
> +static void icl_enable_phy_clock_gating(struct intel_digital_port
> *dig_port)
> +{
> + struct drm_i915_private *dev_priv = to_i915(dig_port-
> >base.base.dev);
> + enum port port = dig_port->base.port;
> + enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> + i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port,
> 1) };
> + u32 val;
> + int i;
> +
> + if (tc_port == PORT_TC_NONE)
> + return;
> +
> + for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
> + val = I915_READ(mg_regs[i]);
> + val |= MG_DP_MODE_CFG_TR2PWR_GATING |
> + MG_DP_MODE_CFG_TRPWR_GATING |
> + MG_DP_MODE_CFG_CLNPWR_GATING |
> + MG_DP_MODE_CFG_DIGPWR_GATING |
> + MG_DP_MODE_CFG_GAONPWR_GATING;
> + I915_WRITE(mg_regs[i], val);
> + }
> +
> + val = I915_READ(MG_MISC_SUS0(tc_port));
> + val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
> + MG_MISC_SUS0_CFG_TR2PWR_GATING |
> + MG_MISC_SUS0_CFG_CL2PWR_GATING |
> + MG_MISC_SUS0_CFG_GAONPWR_GATING |
> + MG_MISC_SUS0_CFG_TRPWR_GATING |
> + MG_MISC_SUS0_CFG_CL1PWR_GATING |
> + MG_MISC_SUS0_CFG_DGPWR_GATING;
> + I915_WRITE(MG_MISC_SUS0(tc_port), val);
> +}
> +
> +static void icl_disable_phy_clock_gating(struct intel_digital_port
> *dig_port)
> +{
> + struct drm_i915_private *dev_priv = to_i915(dig_port-
> >base.base.dev);
> + enum port port = dig_port->base.port;
> + enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> + i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port,
> 1) };
> + u32 val;
> + int i;
> +
> + if (tc_port == PORT_TC_NONE)
> + return;
> +
> + for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
> + val = I915_READ(mg_regs[i]);
> + val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
> + MG_DP_MODE_CFG_TRPWR_GATING |
> + MG_DP_MODE_CFG_CLNPWR_GATING |
> + MG_DP_MODE_CFG_DIGPWR_GATING |
> + MG_DP_MODE_CFG_GAONPWR_GATING);
> + I915_WRITE(mg_regs[i], val);
> + }
> +
> + val = I915_READ(MG_MISC_SUS0(tc_port));
> + val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
> + MG_MISC_SUS0_CFG_TR2PWR_GATING |
> + MG_MISC_SUS0_CFG_CL2PWR_GATING |
> + MG_MISC_SUS0_CFG_GAONPWR_GATING |
> + MG_MISC_SUS0_CFG_TRPWR_GATING |
> + MG_MISC_SUS0_CFG_CL1PWR_GATING |
> + MG_MISC_SUS0_CFG_DGPWR_GATING);
> + I915_WRITE(MG_MISC_SUS0(tc_port), val);
> +}
> +
> static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> const struct intel_crtc_state
> *crtc_state,
> const struct drm_connector_state
> *conn_state)
> @@ -2978,6 +3044,8 @@ static void intel_ddi_pre_enable_hdmi(struct
> intel_encoder *encoder,
>
> intel_display_power_get(dev_priv, dig_port-
> >ddi_io_power_domain);
>
> + icl_disable_phy_clock_gating(dig_port);
> +
> if (IS_ICELAKE(dev_priv))
> icl_ddi_vswing_sequence(encoder, crtc_state-
> >port_clock,
> level, INTEL_OUTPUT_HDMI);
> @@ -2988,6 +3056,8 @@ static void intel_ddi_pre_enable_hdmi(struct
> intel_encoder *encoder,
> else
> intel_prepare_hdmi_ddi_buffers(encoder, level);
>
> + icl_enable_phy_clock_gating(dig_port);
> +
> if (IS_GEN9_BC(dev_priv))
> skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c
> b/drivers/gpu/drm/i915/intel_dp.c
> index b39b4bda8e40..127fc82902c6 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -307,72 +307,6 @@ void icl_program_mg_dp_mode(struct intel_dp
> *intel_dp)
> I915_WRITE(MG_DP_MODE(port, 1), ln1);
> }
>
> -void icl_enable_phy_clock_gating(struct intel_digital_port
> *dig_port)
> -{
> - struct drm_i915_private *dev_priv = to_i915(dig_port-
> >base.base.dev);
> - enum port port = dig_port->base.port;
> - enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> - i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port,
> 1) };
> - u32 val;
> - int i;
> -
> - if (tc_port == PORT_TC_NONE)
> - return;
> -
> - for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
> - val = I915_READ(mg_regs[i]);
> - val |= MG_DP_MODE_CFG_TR2PWR_GATING |
> - MG_DP_MODE_CFG_TRPWR_GATING |
> - MG_DP_MODE_CFG_CLNPWR_GATING |
> - MG_DP_MODE_CFG_DIGPWR_GATING |
> - MG_DP_MODE_CFG_GAONPWR_GATING;
> - I915_WRITE(mg_regs[i], val);
> - }
> -
> - val = I915_READ(MG_MISC_SUS0(tc_port));
> - val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
> - MG_MISC_SUS0_CFG_TR2PWR_GATING |
> - MG_MISC_SUS0_CFG_CL2PWR_GATING |
> - MG_MISC_SUS0_CFG_GAONPWR_GATING |
> - MG_MISC_SUS0_CFG_TRPWR_GATING |
> - MG_MISC_SUS0_CFG_CL1PWR_GATING |
> - MG_MISC_SUS0_CFG_DGPWR_GATING;
> - I915_WRITE(MG_MISC_SUS0(tc_port), val);
> -}
> -
> -void icl_disable_phy_clock_gating(struct intel_digital_port
> *dig_port)
> -{
> - struct drm_i915_private *dev_priv = to_i915(dig_port-
> >base.base.dev);
> - enum port port = dig_port->base.port;
> - enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> - i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port,
> 1) };
> - u32 val;
> - int i;
> -
> - if (tc_port == PORT_TC_NONE)
> - return;
> -
> - for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
> - val = I915_READ(mg_regs[i]);
> - val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
> - MG_DP_MODE_CFG_TRPWR_GATING |
> - MG_DP_MODE_CFG_CLNPWR_GATING |
> - MG_DP_MODE_CFG_DIGPWR_GATING |
> - MG_DP_MODE_CFG_GAONPWR_GATING);
> - I915_WRITE(mg_regs[i], val);
> - }
> -
> - val = I915_READ(MG_MISC_SUS0(tc_port));
> - val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
> - MG_MISC_SUS0_CFG_TR2PWR_GATING |
> - MG_MISC_SUS0_CFG_CL2PWR_GATING |
> - MG_MISC_SUS0_CFG_GAONPWR_GATING |
> - MG_MISC_SUS0_CFG_TRPWR_GATING |
> - MG_MISC_SUS0_CFG_CL1PWR_GATING |
> - MG_MISC_SUS0_CFG_DGPWR_GATING);
> - I915_WRITE(MG_MISC_SUS0(tc_port), val);
> -}
> -
> int
> intel_dp_max_data_rate(int max_link_clock, int max_lanes)
> {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 191c26e17f2d..d0be59599e23 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1820,8 +1820,6 @@ void intel_edp_drrs_invalidate(struct
> drm_i915_private *dev_priv,
> void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
> unsigned int frontbuffer_bits);
> void icl_program_mg_dp_mode(struct intel_dp *intel_dp);
> -void icl_enable_phy_clock_gating(struct intel_digital_port
> *dig_port);
> -void icl_disable_phy_clock_gating(struct intel_digital_port
> *dig_port);
>
> void
> intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
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