Need to do some extra work at PLL disable time to allow HDMI to come
back up on the next mode set.
v2: take dpio lock around update - jbarnes
only do WA on VLV -jbarnes
Signed-off-by: Jesse Barnes <jbar...@virtuousgeek.org>
Signed-off-by: Vijay Purushothaman <vijay.a.purushotha...@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 2bc8ce7..c0cb254 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1492,6 +1492,14 @@ static void intel_disable_pll(struct drm_i915_private
*dev_priv, enum pipe pipe)
int reg;
u32 val;
+ if (IS_VALLEYVIEW(dev_priv->dev)) {
+ mutex_lock(&dev_priv->dpio_lock);
+ // Flicker WA for HDMI
+ intel_dpio_write(dev_priv, 0x8200, 0x00000000);
+ intel_dpio_write(dev_priv, 0x8204, 0x00e00060);
+ mutex_unlock(&dev_priv->dpio_lock);
+ }
+
/* Don't disable pipe A or pipe A PLLs if needed */
if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
return;
@@ -4299,6 +4307,12 @@ static void vlv_update_pll(struct drm_crtc *crtc,
* In Valleyview PLL and program lane counter registers are exposed
* through DPIO interface
*/
+
+ // program DD1 Tx lane resets sets to default
+ // WA for HDMI flicker issue
+ intel_dpio_write(dev_priv, 0x8200, 0x10080);
+ intel_dpio_write(dev_priv, 0x8204, 0x00600060);
+
mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
mdiv |= ((bestn << DPIO_N_SHIFT));
--
1.7.9.5
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