[Intel-gfx] [PATCH 6/9] drm/i915/psr: Check if source supports sink specific SU granularity

[José Roberto de Souza]

According to eDP spec, sink can required specific selective update
granularity that source must comply.
Here caching the value if required and checking source supports it.

Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
Signed-off-by: José Roberto de Souza <jose.so...@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h  |  1 +
 drivers/gpu/drm/i915/intel_psr.c | 32 ++++++++++++++++++++++++++++++++
 2 files changed, 33 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f763b30f98d9..cbcd85af95bf 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -506,6 +506,7 @@ struct i915_psr {
        ktime_t last_exit;
        bool sink_not_reliable;
        bool irq_aux_error;
+       u16 su_x_granularity;
 };
 
 enum intel_pch {
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 7607a58a6ec0..9215c9052381 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -257,6 +257,21 @@ static u8 intel_dp_get_sink_sync_latency(struct intel_dp 
*intel_dp)
        return val;
 }
 
+static u16 intel_dp_get_su_x_granulartiy(struct intel_dp *intel_dp)
+{
+       u16 val = 0;
+       ssize_t r;
+
+       if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED))
+               return val;
+
+       r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &val, 2);
+       if (r != 2)
+               DRM_WARN("Unable to read DP_PSR2_SU_X_GRANULARITY\n");
+
+       return val;
+}
+
 void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 {
        struct drm_i915_private *dev_priv =
@@ -311,6 +326,8 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
                if (dev_priv->psr.sink_psr2_support) {
                        dev_priv->psr.colorimetry_support =
                                intel_dp_get_colorimetry_status(intel_dp);
+                       dev_priv->psr.su_x_granularity =
+                               intel_dp_get_su_x_granulartiy(intel_dp);
                }
        }
 }
@@ -525,6 +542,21 @@ static bool intel_psr2_config_valid(struct intel_dp 
*intel_dp,
                return false;
        }
 
+       if (dev_priv->psr.su_x_granularity) {
+               /*
+                * HW will always send full lines in SU blocks, so X will
+                * always be 0 and we only need to check the width to validate
+                * horizontal granularity.
+                * About vertical granularity HW works by SU blocks starting
+                * at each 4 lines with height of 4 lines, what eDP states
+                * that sink should support.
+                */
+               if (crtc_hdisplay % dev_priv->psr.su_x_granularity) {
+                       DRM_DEBUG_KMS("PSR2 not enabled, HW can not match sink 
SU granularity requirement\n");
+                       return false;
+               }
+       }
+
        return true;
 }
 
-- 
2.19.2

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