On Wed, 2019-01-16 at 11:15 +0200, Jani Nikula wrote: > Mixed C99 and kernel types use is getting ugly. Prefer kernel types. > > sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g' > > Minor checkpatch fixes sprinkled on top of the changed lines.
Reviewed-by: José Roberto de Souza <jose.so...@intel.com>
>
> Signed-off-by: Jani Nikula <jani.nik...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_gem.c | 14 +++++++-------
> drivers/gpu/drm/i915/i915_gem_fence_reg.c | 8 ++++----
> drivers/gpu/drm/i915/i915_gpu_error.c | 10 +++++-----
> drivers/gpu/drm/i915/i915_perf.c | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 4 ++--
> drivers/gpu/drm/i915/intel_atomic.c | 4 ++--
> drivers/gpu/drm/i915/intel_atomic_plane.c | 4 ++--
> drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
> drivers/gpu/drm/i915/intel_dpio_phy.c | 18 +++++++++---------
> drivers/gpu/drm/i915/intel_engine_cs.c | 12 ++++++------
> drivers/gpu/drm/i915/intel_fbc.c | 2 +-
> drivers/gpu/drm/i915/intel_fifo_underrun.c | 12 ++++++------
> drivers/gpu/drm/i915/intel_hdcp.c | 4 ++--
> drivers/gpu/drm/i915/intel_lrc.c | 2 +-
> drivers/gpu/drm/i915/intel_pipe_crc.c | 18 +++++++++---------
> drivers/gpu/drm/i915/intel_psr.c | 6 +++---
> drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +-
> drivers/gpu/drm/i915/intel_runtime_pm.c | 20 ++++++++++----------
> 18 files changed, 72 insertions(+), 72 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c
> b/drivers/gpu/drm/i915/i915_gem.c
> index 80264cb9ca7f..d15f7200c0e7 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -710,8 +710,8 @@ void i915_gem_object_free(struct
> drm_i915_gem_object *obj)
> static int
> i915_gem_create(struct drm_file *file,
> struct drm_i915_private *dev_priv,
> - uint64_t size,
> - uint32_t *handle_p)
> + u64 size,
> + u32 *handle_p)
> {
> struct drm_i915_gem_object *obj;
> int ret;
> @@ -1570,8 +1570,8 @@ i915_gem_set_domain_ioctl(struct drm_device
> *dev, void *data,
> {
> struct drm_i915_gem_set_domain *args = data;
> struct drm_i915_gem_object *obj;
> - uint32_t read_domains = args->read_domains;
> - uint32_t write_domain = args->write_domain;
> + u32 read_domains = args->read_domains;
> + u32 write_domain = args->write_domain;
> int err;
>
> /* Only handle setting domains to types used by the CPU. */
> @@ -1753,7 +1753,7 @@ i915_gem_mmap_ioctl(struct drm_device *dev,
> void *data,
> if (IS_ERR((void *)addr))
> return addr;
>
> - args->addr_ptr = (uint64_t) addr;
> + args->addr_ptr = (u64)addr;
>
> return 0;
> }
> @@ -2155,8 +2155,8 @@ static void
> i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
> int
> i915_gem_mmap_gtt(struct drm_file *file,
> struct drm_device *dev,
> - uint32_t handle,
> - uint64_t *offset)
> + u32 handle,
> + u64 *offset)
> {
> struct drm_i915_gem_object *obj;
> int ret;
> diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> index f7947d89cf45..46e259661294 100644
> --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> @@ -555,8 +555,8 @@ void i915_gem_restore_fences(struct
> drm_i915_private *dev_priv)
> void
> i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv)
> {
> - uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
> - uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
> + u32 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
> + u32 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
>
> if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) {
> /*
> @@ -579,7 +579,7 @@ i915_gem_detect_bit_6_swizzle(struct
> drm_i915_private *dev_priv)
> swizzle_y = I915_BIT_6_SWIZZLE_NONE;
> }
> } else {
> - uint32_t dimm_c0, dimm_c1;
> + u32 dimm_c0, dimm_c1;
> dimm_c0 = I915_READ(MAD_DIMM_C0);
> dimm_c1 = I915_READ(MAD_DIMM_C1);
> dimm_c0 &= MAD_DIMM_A_SIZE_MASK |
> MAD_DIMM_B_SIZE_MASK;
> @@ -611,7 +611,7 @@ i915_gem_detect_bit_6_swizzle(struct
> drm_i915_private *dev_priv)
> swizzle_y = I915_BIT_6_SWIZZLE_NONE;
> } else if (IS_MOBILE(dev_priv) ||
> IS_I915G(dev_priv) || IS_I945G(dev_priv)) {
> - uint32_t dcc;
> + u32 dcc;
>
> /* On 9xx chipsets, channel interleave by the CPU is
> * determined by DCC. For single-channel, neither the
> CPU
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
> b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 5eaf586c4d48..1f8e80e31b49 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -1082,7 +1082,7 @@ i915_error_object_create(struct
> drm_i915_private *i915,
> /* The error capture is special as tries to run underneath the
> normal
> * locking rules - so we use the raw version of the i915_gem_active
> lookup.
> */
> -static inline uint32_t
> +static inline u32
> __active_get_seqno(struct i915_gem_active *active)
> {
> struct i915_request *request;
> @@ -1153,11 +1153,11 @@ static u32 capture_error_bo(struct
> drm_i915_error_buffer *err,
> *
> * It's only a small step better than a random number in its current
> form.
> */
> -static uint32_t i915_error_generate_code(struct drm_i915_private
> *dev_priv,
> - struct i915_gpu_state *error,
> - int *engine_id)
> +static u32 i915_error_generate_code(struct drm_i915_private
> *dev_priv,
> + struct i915_gpu_state *error,
> + int *engine_id)
> {
> - uint32_t error_code = 0;
> + u32 error_code = 0;
> int i;
>
> /* IPEHR would be an ideal way to detect errors, as it's the
> gross
> diff --git a/drivers/gpu/drm/i915/i915_perf.c
> b/drivers/gpu/drm/i915/i915_perf.c
> index faff6cf1aaa1..727118301f91 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -3021,7 +3021,7 @@ static bool chv_is_valid_mux_addr(struct
> drm_i915_private *dev_priv, u32 addr)
> (addr >= 0x182300 && addr <= 0x1823A4);
> }
>
> -static uint32_t mask_reg_value(u32 reg, u32 val)
> +static u32 mask_reg_value(u32 reg, u32 val)
> {
> /* HALF_SLICE_CHICKEN2 is programmed with a the
> * WaDisableSTUnitPowerOptimization workaround. Make sure the
> value
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index fad5a9e8b44d..9a1340cfda6c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -117,14 +117,14 @@
> */
>
> typedef struct {
> - uint32_t reg;
> + u32 reg;
> } i915_reg_t;
>
> #define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
>
> #define INVALID_MMIO_REG _MMIO(0)
>
> -static inline uint32_t i915_mmio_reg_offset(i915_reg_t reg)
> +static inline u32 i915_mmio_reg_offset(i915_reg_t reg)
> {
> return reg.reg;
> }
> diff --git a/drivers/gpu/drm/i915/intel_atomic.c
> b/drivers/gpu/drm/i915/intel_atomic.c
> index d8dbc9980281..16263add3cdd 100644
> --- a/drivers/gpu/drm/i915/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/intel_atomic.c
> @@ -46,7 +46,7 @@
> int intel_digital_connector_atomic_get_property(struct drm_connector
> *connector,
> const struct
> drm_connector_state *state,
> struct drm_property
> *property,
> - uint64_t *val)
> + u64 *val)
> {
> struct drm_device *dev = connector->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -78,7 +78,7 @@ int
> intel_digital_connector_atomic_get_property(struct drm_connector
> *connector,
> int intel_digital_connector_atomic_set_property(struct drm_connector
> *connector,
> struct
> drm_connector_state *state,
> struct drm_property
> *property,
> - uint64_t val)
> + u64 val)
> {
> struct drm_device *dev = connector->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/intel_atomic_plane.c
> index 683a75dad4fb..9a2fdc77ebcb 100644
> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> @@ -311,7 +311,7 @@ int
> intel_plane_atomic_get_property(struct drm_plane *plane,
> const struct drm_plane_state *state,
> struct drm_property *property,
> - uint64_t *val)
> + u64 *val)
> {
> DRM_DEBUG_KMS("Unknown property [PROP:%d:%s]\n",
> property->base.id, property->name);
> @@ -334,7 +334,7 @@ int
> intel_plane_atomic_set_property(struct drm_plane *plane,
> struct drm_plane_state *state,
> struct drm_property *property,
> - uint64_t val)
> + u64 val)
> {
> DRM_DEBUG_KMS("Unknown property [PROP:%d:%s]\n",
> property->base.id, property->name);
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
> b/drivers/gpu/drm/i915/intel_dp_mst.c
> index a19699023db1..f90041cb336d 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -247,7 +247,7 @@ static void intel_mst_pre_enable_dp(struct
> intel_encoder *encoder,
> struct intel_connector *connector =
> to_intel_connector(conn_state->connector);
> int ret;
> - uint32_t temp;
> + u32 temp;
>
> /* MST encoders are bound to a crtc, not to a connector,
> * force the mapping here for get_hw_state.
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c
> b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index 3c7f10d17658..95cb8b154f87 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -413,7 +413,7 @@ static void _bxt_ddi_phy_init(struct
> drm_i915_private *dev_priv,
> }
>
> if (phy_info->rcomp_phy != -1) {
> - uint32_t grc_code;
> + u32 grc_code;
>
> bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy);
>
> @@ -445,7 +445,7 @@ static void _bxt_ddi_phy_init(struct
> drm_i915_private *dev_priv,
> void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum
> dpio_phy phy)
> {
> const struct bxt_ddi_phy_info *phy_info;
> - uint32_t val;
> + u32 val;
>
> phy_info = bxt_get_phy_info(dev_priv, phy);
>
> @@ -515,7 +515,7 @@ bool bxt_ddi_phy_verify_state(struct
> drm_i915_private *dev_priv,
> enum dpio_phy phy)
> {
> const struct bxt_ddi_phy_info *phy_info;
> - uint32_t mask;
> + u32 mask;
> bool ok;
>
> phy_info = bxt_get_phy_info(dev_priv, phy);
> @@ -567,8 +567,8 @@ bool bxt_ddi_phy_verify_state(struct
> drm_i915_private *dev_priv,
> #undef _CHK
> }
>
> -uint8_t
> -bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count)
> +u8
> +bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count)
> {
> switch (lane_count) {
> case 1:
> @@ -585,7 +585,7 @@ bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t
> lane_count)
> }
>
> void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
> - uint8_t lane_lat_optim_mask)
> + u8 lane_lat_optim_mask)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> enum port port = encoder->port;
> @@ -610,7 +610,7 @@ void bxt_ddi_phy_set_lane_optim_mask(struct
> intel_encoder *encoder,
> }
> }
>
> -uint8_t
> +u8
> bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> @@ -618,7 +618,7 @@ bxt_ddi_phy_get_lane_lat_optim_mask(struct
> intel_encoder *encoder)
> enum dpio_phy phy;
> enum dpio_channel ch;
> int lane;
> - uint8_t mask;
> + u8 mask;
>
> bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
>
> @@ -739,7 +739,7 @@ void chv_data_lane_soft_reset(struct
> intel_encoder *encoder,
> enum dpio_channel ch =
> vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> enum pipe pipe = crtc->pipe;
> - uint32_t val;
> + u32 val;
>
> val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
> if (reset)
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
> b/drivers/gpu/drm/i915/intel_engine_cs.c
> index bf4dae2649ab..59216dd8bfa1 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -799,15 +799,15 @@ u32 intel_calculate_mcr_s_ss_select(struct
> drm_i915_private *dev_priv)
> return mcr_s_ss_select;
> }
>
> -static inline uint32_t
> +static inline u32
> read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
> int subslice, i915_reg_t reg)
> {
> - uint32_t mcr_slice_subslice_mask;
> - uint32_t mcr_slice_subslice_select;
> - uint32_t default_mcr_s_ss_select;
> - uint32_t mcr;
> - uint32_t ret;
> + u32 mcr_slice_subslice_mask;
> + u32 mcr_slice_subslice_select;
> + u32 default_mcr_s_ss_select;
> + u32 mcr;
> + u32 ret;
> enum forcewake_domains fw_domains;
>
> if (INTEL_GEN(dev_priv) >= 11) {
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c
> b/drivers/gpu/drm/i915/intel_fbc.c
> index ccd5e110a19c..ec72be4b7a7b 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -594,7 +594,7 @@ static bool stride_is_valid(struct
> drm_i915_private *dev_priv,
> }
>
> static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
> - uint32_t pixel_format)
> + u32 pixel_format)
> {
> switch (pixel_format) {
> case DRM_FORMAT_XRGB8888:
> diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c
> b/drivers/gpu/drm/i915/intel_fifo_underrun.c
> index 9b39975c8389..3b9285130ef5 100644
> --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c
> +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c
> @@ -127,8 +127,8 @@ static void
> ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
> enum pipe pipe, bool
> enable)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> - uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
> - DE_PIPEB_FIFO_UNDERRUN;
> + u32 bit = (pipe == PIPE_A) ?
> + DE_PIPEA_FIFO_UNDERRUN : DE_PIPEB_FIFO_UNDERRUN;
>
> if (enable)
> ilk_enable_display_irq(dev_priv, bit);
> @@ -140,7 +140,7 @@ static void ivybridge_check_fifo_underruns(struct
> intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> - uint32_t err_int = I915_READ(GEN7_ERR_INT);
> + u32 err_int = I915_READ(GEN7_ERR_INT);
>
> lockdep_assert_held(&dev_priv->irq_lock);
>
> @@ -193,8 +193,8 @@ static void
> ibx_set_fifo_underrun_reporting(struct drm_device *dev,
> bool enable)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> - uint32_t bit = (pch_transcoder == PIPE_A) ?
> - SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
> + u32 bit = (pch_transcoder == PIPE_A) ?
> + SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
>
> if (enable)
> ibx_enable_display_interrupt(dev_priv, bit);
> @@ -206,7 +206,7 @@ static void cpt_check_pch_fifo_underruns(struct
> intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pch_transcoder = crtc->pipe;
> - uint32_t serr_int = I915_READ(SERR_INT);
> + u32 serr_int = I915_READ(SERR_INT);
>
> lockdep_assert_held(&dev_priv->irq_lock);
>
> diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
> b/drivers/gpu/drm/i915/intel_hdcp.c
> index 3fcb3b775948..ce7ba3a9c000 100644
> --- a/drivers/gpu/drm/i915/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/intel_hdcp.c
> @@ -838,8 +838,8 @@ void intel_hdcp_atomic_check(struct drm_connector
> *connector,
> struct drm_connector_state *old_state,
> struct drm_connector_state *new_state)
> {
> - uint64_t old_cp = old_state->content_protection;
> - uint64_t new_cp = new_state->content_protection;
> + u64 old_cp = old_state->content_protection;
> + u64 new_cp = new_state->content_protection;
> struct drm_crtc_state *crtc_state;
>
> if (!new_state->crtc) {
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> b/drivers/gpu/drm/i915/intel_lrc.c
> index 608458b92db3..1d4bebcd4c8b 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -2608,7 +2608,7 @@ static int
> execlists_context_deferred_alloc(struct i915_gem_context *ctx,
> {
> struct drm_i915_gem_object *ctx_obj;
> struct i915_vma *vma;
> - uint32_t context_size;
> + u32 context_size;
> struct intel_ring *ring;
> struct i915_timeline *timeline;
> int ret;
> diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c
> b/drivers/gpu/drm/i915/intel_pipe_crc.c
> index 56d614b02302..a8554dc4f196 100644
> --- a/drivers/gpu/drm/i915/intel_pipe_crc.c
> +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
> @@ -44,7 +44,7 @@ static const char * const pipe_crc_sources[] = {
> };
>
> static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
> - uint32_t *val)
> + u32 *val)
> {
> if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
> *source = INTEL_PIPE_CRC_SOURCE_PIPE;
> @@ -120,7 +120,7 @@ static int i9xx_pipe_crc_auto_source(struct
> drm_i915_private *dev_priv,
> static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
> enum pipe pipe,
> enum intel_pipe_crc_source *source,
> - uint32_t *val)
> + u32 *val)
> {
> bool need_stable_symbols = false;
>
> @@ -165,7 +165,7 @@ static int vlv_pipe_crc_ctl_reg(struct
> drm_i915_private *dev_priv,
> * - DisplayPort scrambling: used for EMI reduction
> */
> if (need_stable_symbols) {
> - uint32_t tmp = I915_READ(PORT_DFT2_G4X);
> + u32 tmp = I915_READ(PORT_DFT2_G4X);
>
> tmp |= DC_BALANCE_RESET_VLV;
> switch (pipe) {
> @@ -190,7 +190,7 @@ static int vlv_pipe_crc_ctl_reg(struct
> drm_i915_private *dev_priv,
> static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
> enum pipe pipe,
> enum intel_pipe_crc_source *source,
> - uint32_t *val)
> + u32 *val)
> {
> bool need_stable_symbols = false;
>
> @@ -244,7 +244,7 @@ static int i9xx_pipe_crc_ctl_reg(struct
> drm_i915_private *dev_priv,
> * - DisplayPort scrambling: used for EMI reduction
> */
> if (need_stable_symbols) {
> - uint32_t tmp = I915_READ(PORT_DFT2_G4X);
> + u32 tmp = I915_READ(PORT_DFT2_G4X);
>
> WARN_ON(!IS_G4X(dev_priv));
>
> @@ -265,7 +265,7 @@ static int i9xx_pipe_crc_ctl_reg(struct
> drm_i915_private *dev_priv,
> static void vlv_undo_pipe_scramble_reset(struct drm_i915_private
> *dev_priv,
> enum pipe pipe)
> {
> - uint32_t tmp = I915_READ(PORT_DFT2_G4X);
> + u32 tmp = I915_READ(PORT_DFT2_G4X);
>
> switch (pipe) {
> case PIPE_A:
> @@ -289,7 +289,7 @@ static void vlv_undo_pipe_scramble_reset(struct
> drm_i915_private *dev_priv,
> static void g4x_undo_pipe_scramble_reset(struct drm_i915_private
> *dev_priv,
> enum pipe pipe)
> {
> - uint32_t tmp = I915_READ(PORT_DFT2_G4X);
> + u32 tmp = I915_READ(PORT_DFT2_G4X);
>
> if (pipe == PIPE_A)
> tmp &= ~PIPE_A_SCRAMBLE_RESET;
> @@ -304,7 +304,7 @@ static void g4x_undo_pipe_scramble_reset(struct
> drm_i915_private *dev_priv,
> }
>
> static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
> - uint32_t *val)
> + u32 *val)
> {
> if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
> *source = INTEL_PIPE_CRC_SOURCE_PIPE;
> @@ -392,7 +392,7 @@ static void hsw_pipe_A_crc_wa(struct
> drm_i915_private *dev_priv,
> static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
> enum pipe pipe,
> enum intel_pipe_crc_source *source,
> - uint32_t *val,
> + u32 *val,
> bool set_wa)
> {
> if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 0f6b2b4702e3..8dbf26c212cc 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -230,7 +230,7 @@ void intel_psr_irq_handler(struct
> drm_i915_private *dev_priv, u32 psr_iir)
>
> static bool intel_dp_get_colorimetry_status(struct intel_dp
> *intel_dp)
> {
> - uint8_t dprx = 0;
> + u8 dprx = 0;
>
> if (drm_dp_dpcd_readb(&intel_dp->aux,
> DP_DPRX_FEATURE_ENUMERATION_LIST,
> &dprx) != 1)
> @@ -240,7 +240,7 @@ static bool
> intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
>
> static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
> {
> - uint8_t alpm_caps = 0;
> + u8 alpm_caps = 0;
>
> if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
> &alpm_caps) != 1)
> @@ -384,7 +384,7 @@ static void hsw_psr_setup_aux(struct intel_dp
> *intel_dp)
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> u32 aux_clock_divider, aux_ctl;
> int i;
> - static const uint8_t aux_msg[] = {
> + static const u8 aux_msg[] = {
> [0] = DP_AUX_NATIVE_WRITE << 4,
> [1] = DP_SET_POWER >> 8,
> [2] = DP_SET_POWER & 0xff,
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
> b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 3c1366c58cf3..616f6bbb18ad 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -28,7 +28,7 @@ struct i915_sched_attr;
> * workarounds!
> */
> #define CACHELINE_BYTES 64
> -#define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t))
> +#define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(u32))
>
> struct intel_hw_status_page {
> struct i915_vma *vma;
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 79f00610860b..a017a4232c0f 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -903,10 +903,10 @@ void gen9_sanitize_dc_state(struct
> drm_i915_private *dev_priv)
> * back on and register state is restored. This is guaranteed by the
> MMIO write
> * to DC_STATE_EN blocking until the state is restored.
> */
> -static void gen9_set_dc_state(struct drm_i915_private *dev_priv,
> uint32_t state)
> +static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32
> state)
> {
> - uint32_t val;
> - uint32_t mask;
> + u32 val;
> + u32 mask;
>
> if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask))
> state &= dev_priv->csr.allowed_dc_mask;
> @@ -1538,7 +1538,7 @@ static void
> chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
> {
> enum dpio_phy phy;
> enum pipe pipe;
> - uint32_t tmp;
> + u32 tmp;
>
> WARN_ON_ONCE(power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC &&
> power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D);
> @@ -3328,10 +3328,10 @@ sanitize_disable_power_well_option(const
> struct drm_i915_private *dev_priv,
> return 1;
> }
>
> -static uint32_t get_allowed_dc_mask(const struct drm_i915_private
> *dev_priv,
> - int enable_dc)
> +static u32 get_allowed_dc_mask(const struct drm_i915_private
> *dev_priv,
> + int enable_dc)
> {
> - uint32_t mask;
> + u32 mask;
> int requested_dc;
> int max_dc;
>
> @@ -3596,7 +3596,7 @@ static void icl_dbuf_disable(struct
> drm_i915_private *dev_priv)
>
> static void icl_mbus_init(struct drm_i915_private *dev_priv)
> {
> - uint32_t val;
> + u32 val;
>
> val = MBUS_ABOX_BT_CREDIT_POOL1(16) |
> MBUS_ABOX_BT_CREDIT_POOL2(16) |
> @@ -3907,7 +3907,7 @@ static void chv_phy_control_init(struct
> drm_i915_private *dev_priv)
> * current lane status.
> */
> if (cmn_bc->desc->ops->is_enabled(dev_priv, cmn_bc)) {
> - uint32_t status = I915_READ(DPLL(PIPE_A));
> + u32 status = I915_READ(DPLL(PIPE_A));
> unsigned int mask;
>
> mask = status & DPLL_PORTB_READY_MASK;
> @@ -3938,7 +3938,7 @@ static void chv_phy_control_init(struct
> drm_i915_private *dev_priv)
> }
>
> if (cmn_d->desc->ops->is_enabled(dev_priv, cmn_d)) {
> - uint32_t status = I915_READ(DPIO_PHY_STATUS);
> + u32 status = I915_READ(DPIO_PHY_STATUS);
> unsigned int mask;
>
> mask = status & DPLL_PORTD_READY_MASK;
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