From: Swati Sharma <swati2.sha...@intel.com>

In this patch, apart from enabling Y2xx and Y4xx pixel formats
P0xx pixel formats are added too for ICL.

Signed-off-by: Swati Sharma <swati2.sha...@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikk...@gmail.com>
---
 drivers/gpu/drm/i915/intel_display.c | 30 ++++++++++++++++++
 drivers/gpu/drm/i915/intel_sprite.c  | 60 +++++++++++++++++++++++++++++++++++-
 2 files changed, 89 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 0345d04..dc1685c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2683,6 +2683,18 @@ int skl_format_to_fourcc(int format, bool rgb_order, 
bool alpha)
                return DRM_FORMAT_P012;
        case PLANE_CTL_FORMAT_P016:
                return DRM_FORMAT_P016;
+       case PLANE_CTL_FORMAT_Y210:
+               return DRM_FORMAT_Y210;
+       case PLANE_CTL_FORMAT_Y212:
+               return DRM_FORMAT_Y212;
+       case PLANE_CTL_FORMAT_Y216:
+               return DRM_FORMAT_Y216;
+       case PLANE_CTL_FORMAT_Y410:
+               return DRM_FORMAT_Y410;
+       case PLANE_CTL_FORMAT_Y412:
+               return DRM_FORMAT_Y412;
+       case PLANE_CTL_FORMAT_Y416:
+               return DRM_FORMAT_Y416;
        default:
        case PLANE_CTL_FORMAT_XRGB_8888:
                if (rgb_order) {
@@ -3612,6 +3624,18 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
                return PLANE_CTL_FORMAT_P012;
        case DRM_FORMAT_P016:
                return PLANE_CTL_FORMAT_P016;
+       case DRM_FORMAT_Y210:
+               return PLANE_CTL_FORMAT_Y210;
+       case DRM_FORMAT_Y212:
+               return PLANE_CTL_FORMAT_Y212;
+       case DRM_FORMAT_Y216:
+               return PLANE_CTL_FORMAT_Y216;
+       case DRM_FORMAT_Y410:
+               return PLANE_CTL_FORMAT_Y410;
+       case DRM_FORMAT_Y412:
+               return PLANE_CTL_FORMAT_Y412;
+       case DRM_FORMAT_Y416:
+               return PLANE_CTL_FORMAT_Y416;
        default:
                MISSING_CASE(pixel_format);
        }
@@ -5164,6 +5188,12 @@ static int skl_update_scaler_plane(struct 
intel_crtc_state *crtc_state,
        case DRM_FORMAT_P010:
        case DRM_FORMAT_P012:
        case DRM_FORMAT_P016:
+       case DRM_FORMAT_Y210:
+       case DRM_FORMAT_Y212:
+       case DRM_FORMAT_Y216:
+       case DRM_FORMAT_Y410:
+       case DRM_FORMAT_Y412:
+       case DRM_FORMAT_Y416:
                break;
        default:
                DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 
0x%x\n",
diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index a120266..af147e7 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1803,6 +1803,27 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device 
*dev, void *data,
        DRM_FORMAT_VYUY,
 };
 
+static const uint32_t icl_plane_formats[] = {
+       DRM_FORMAT_C8,
+       DRM_FORMAT_RGB565,
+       DRM_FORMAT_XRGB8888,
+       DRM_FORMAT_XBGR8888,
+       DRM_FORMAT_ARGB8888,
+       DRM_FORMAT_ABGR8888,
+       DRM_FORMAT_XRGB2101010,
+       DRM_FORMAT_XBGR2101010,
+       DRM_FORMAT_YUYV,
+       DRM_FORMAT_YVYU,
+       DRM_FORMAT_UYVY,
+       DRM_FORMAT_VYUY,
+       DRM_FORMAT_Y210,
+       DRM_FORMAT_Y212,
+       DRM_FORMAT_Y216,
+       DRM_FORMAT_Y410,
+       DRM_FORMAT_Y412,
+       DRM_FORMAT_Y416,
+};
+
 static const u32 skl_planar_formats[] = {
        DRM_FORMAT_C8,
        DRM_FORMAT_RGB565,
@@ -1838,6 +1859,31 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device 
*dev, void *data,
        DRM_FORMAT_P016,
 };
 
+static const uint32_t icl_planar_formats[] = {
+       DRM_FORMAT_C8,
+       DRM_FORMAT_RGB565,
+       DRM_FORMAT_XRGB8888,
+       DRM_FORMAT_XBGR8888,
+       DRM_FORMAT_ARGB8888,
+       DRM_FORMAT_ABGR8888,
+       DRM_FORMAT_XRGB2101010,
+       DRM_FORMAT_XBGR2101010,
+       DRM_FORMAT_YUYV,
+       DRM_FORMAT_YVYU,
+       DRM_FORMAT_UYVY,
+       DRM_FORMAT_VYUY,
+       DRM_FORMAT_NV12,
+       DRM_FORMAT_P010,
+       DRM_FORMAT_P012,
+       DRM_FORMAT_P016,
+       DRM_FORMAT_Y210,
+       DRM_FORMAT_Y212,
+       DRM_FORMAT_Y216,
+       DRM_FORMAT_Y410,
+       DRM_FORMAT_Y412,
+       DRM_FORMAT_Y416,
+};
+
 static const u64 skl_plane_format_modifiers_noccs[] = {
        I915_FORMAT_MOD_Yf_TILED,
        I915_FORMAT_MOD_Y_TILED,
@@ -1980,6 +2026,12 @@ static bool skl_plane_format_mod_supported(struct 
drm_plane *_plane,
        case DRM_FORMAT_P010:
        case DRM_FORMAT_P012:
        case DRM_FORMAT_P016:
+       case DRM_FORMAT_Y210:
+       case DRM_FORMAT_Y212:
+       case DRM_FORMAT_Y216:
+       case DRM_FORMAT_Y410:
+       case DRM_FORMAT_Y412:
+       case DRM_FORMAT_Y416:
                if (modifier == I915_FORMAT_MOD_Yf_TILED)
                        return true;
                /* fall through */
@@ -2120,13 +2172,19 @@ struct intel_plane *
                plane->update_slave = icl_update_slave;
 
        if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
-               if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+               if (INTEL_GEN(dev_priv) >= 11) {
+                       formats = icl_planar_formats;
+                       num_formats = ARRAY_SIZE(icl_planar_formats);
+               } else if (INTEL_GEN(dev_priv) == 10 || 
IS_GEMINILAKE(dev_priv)) {
                        formats = glk_planar_formats;
                        num_formats = ARRAY_SIZE(glk_planar_formats);
                } else {
                        formats = skl_planar_formats;
                        num_formats = ARRAY_SIZE(skl_planar_formats);
                }
+       } else if (INTEL_GEN(dev_priv) >= 11) {
+               formats = icl_plane_formats;
+               num_formats = ARRAY_SIZE(icl_plane_formats);
        } else {
                formats = skl_plane_formats;
                num_formats = ARRAY_SIZE(skl_plane_formats);
-- 
1.9.1

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