On Thu, Nov 29, 2018 at 07:55:04PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrj...@linux.intel.com>
>
> As there are no upstream drivers for VED or ISP let's just
> assert that they are power gated. Otherwise they would
> prevent s0ix entry.
>
> For ISP this is only relevant when it is not exposed as a
> PCI device and instead is a subordinate of the gunit. When
> exposed as a PCI device it will be handled by the
> atomisp2_pm driver.
>
> On my VLV FFRD8 board the firmware power gates both of these
> by default. Let's assume that is always the case and just
> WARN if we ever encounter something different.
>
> Cc: Hans de Goede <hdego...@redhat.com>
> Cc: Alan Cox <a...@linux.intel.com>
> Cc: Andy Shevchenko <andriy.shevche...@linux.intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
Reviewed-by: Imre Deak <imre.d...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 28 +++++++++++++++++++++
> drivers/gpu/drm/i915/intel_runtime_pm.c | 33 +++++++++++++++++++++++++
> 2 files changed, 61 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 42d25872ecfe..c2ecac4cb51b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1020,6 +1020,31 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> /* See configdb bunit SB addr map */
> #define BUNIT_REG_BISOC 0x11
>
> +/* PUNIT_REG_*SSPM0 */
> +#define _SSPM0_SSC(val) ((val) << 0)
> +#define SSPM0_SSC_MASK _SSPM0_SSC(0x3)
> +#define SSPM0_SSC_PWR_ON _SSPM0_SSC(0x0)
> +#define SSPM0_SSC_CLK_GATE _SSPM0_SSC(0x1)
> +#define SSPM0_SSC_RESET _SSPM0_SSC(0x2)
> +#define SSPM0_SSC_PWR_GATE _SSPM0_SSC(0x3)
> +#define _SSPM0_SSS(val) ((val) << 24)
> +#define SSPM0_SSS_MASK _SSPM0_SSS(0x3)
> +#define SSPM0_SSS_PWR_ON _SSPM0_SSS(0x0)
> +#define SSPM0_SSS_CLK_GATE _SSPM0_SSS(0x1)
> +#define SSPM0_SSS_RESET _SSPM0_SSS(0x2)
> +#define SSPM0_SSS_PWR_GATE _SSPM0_SSS(0x3)
> +
> +/* PUNIT_REG_*SSPM1 */
> +#define SSPM1_FREQSTAT_SHIFT 24
> +#define SSPM1_FREQSTAT_MASK (0x1f <<
> SSPM1_FREQSTAT_SHIFT)
> +#define SSPM1_FREQGUAR_SHIFT 8
> +#define SSPM1_FREQGUAR_MASK (0x1f <<
> SSPM1_FREQGUAR_SHIFT)
> +#define SSPM1_FREQ_SHIFT 0
> +#define SSPM1_FREQ_MASK (0x1f << SSPM1_FREQ_SHIFT)
> +
> +#define PUNIT_REG_VEDSSPM0 0x32
> +#define PUNIT_REG_VEDSSPM1 0x33
> +
> #define PUNIT_REG_DSPSSPM 0x36
> #define DSPFREQSTAT_SHIFT_CHV 24
> #define DSPFREQSTAT_MASK_CHV (0x1f <<
> DSPFREQSTAT_SHIFT_CHV)
> @@ -1045,6 +1070,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
> #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
>
> +#define PUNIT_REG_ISPSSPM0 0x39
> +#define PUNIT_REG_ISPSSPM1 0x3a
> +
> /*
> * i915_power_well_id:
> *
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index af499d4a0c66..416521f45ec7 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -3706,6 +3706,36 @@ static void vlv_cmnlane_wa(struct drm_i915_private
> *dev_priv)
> cmn->desc->ops->disable(dev_priv, cmn);
> }
>
> +static bool vlv_punit_is_power_gated(struct drm_i915_private *dev_priv, u32
> reg0)
> +{
> + bool ret;
> +
> + mutex_lock(&dev_priv->pcu_lock);
> + ret = (vlv_punit_read(dev_priv, reg0) & SSPM0_SSC_MASK) ==
> SSPM0_SSC_PWR_GATE;
> + mutex_unlock(&dev_priv->pcu_lock);
> +
> + return ret;
> +}
> +
> +static void assert_ved_power_gated(struct drm_i915_private *dev_priv)
> +{
> + WARN(!vlv_punit_is_power_gated(dev_priv, PUNIT_REG_VEDSSPM0),
> + "VED not power gated\n");
> +}
> +
> +static void assert_isp_power_gated(struct drm_i915_private *dev_priv)
> +{
> + static const struct pci_device_id isp_ids[] = {
> + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0f38)},
> + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x22b8)},
> + {}
> + };
> +
> + WARN(!pci_dev_present(isp_ids) &&
> + !vlv_punit_is_power_gated(dev_priv, PUNIT_REG_ISPSSPM0),
> + "ISP not power gated\n");
> +}
> +
> static void intel_power_domains_verify_state(struct drm_i915_private
> *dev_priv);
>
> /**
> @@ -3742,10 +3772,13 @@ void intel_power_domains_init_hw(struct
> drm_i915_private *dev_priv, bool resume)
> mutex_lock(&power_domains->lock);
> chv_phy_control_init(dev_priv);
> mutex_unlock(&power_domains->lock);
> + assert_isp_power_gated(dev_priv);
> } else if (IS_VALLEYVIEW(dev_priv)) {
> mutex_lock(&power_domains->lock);
> vlv_cmnlane_wa(dev_priv);
> mutex_unlock(&power_domains->lock);
> + assert_ved_power_gated(dev_priv);
> + assert_isp_power_gated(dev_priv);
> } else if (IS_IVYBRIDGE(dev_priv) || INTEL_GEN(dev_priv) >= 7)
> intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
>
> --
> 2.18.1
>
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